PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 181

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Figure 11-13. Back-to-back PCI burst write operations with 16 data phases which might be generated by the
ICP when writing image data to a PCI-resident video frame buffer.
11.8
11.8.1
The PCI interface does not implement lock#, sbo, and
sbone pins. Consequently, it is possible for both the
DSPCPU and external PCI initiators to write to a critical
memory section simultaneously. Software must imple-
ment policies to guarantee memory coherency.
11.8.2
PNX1300 does not implement the PCI expansion ROM
capability.
Figure 11-12. PCI burst write operation with 16 data phases.
LIMITATIONS
Bus Locking
No Expansion ROM
devsel#
frame#
pci_clk
c/be#
trdy#
irdy#
ad
devsel#
frame#
pci_clk
c/be#
trdy#
irdy#
ad
1
Command
Address
1
2
Command
Address
2
Data 1
3
Data 1
3
Byte Enables
Data 2
Data 15
4
18
Data 3
Data 16
5
11.8.3
The PCI interface does not implement the PCI cacheline-
wrap address mode for external PCI initiators that ac-
cess PNX1300 SDRAM.
11.8.4
Only single-data-phase transactions to configuration and
I/O spaces are supported. The byte-enable signals se-
lect the byte(s) within the addressed word.
11.8.5
External initiators can access PNX1300 MMIO registers
only as full words. The byte-enable signals have no ef-
fect on the data transferred. External initiators must read
and write all four bytes of MMIO registers.
PRELIMINARY SPECIFICATION
19
Byte Enables
Data 4
Data 17
6
20
No Cacheline Wrap Address
Sequence
No Burst for I/O or Configuration
Space
Word-Only MMIO Register Access
Byte Enables
Data 15
17
Data 31
35
Data 16
18
Data 32
36
PCI Interface
11-17