PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 203

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
system Vendor ID Register,”
choice of values.
Table 13-3I
The MM_CONFIG and PLL_RATIOS registers control
the hardware of the MMI and PNX1300 on-chip clock cir-
cuits. These registers are described in detail in
12.6, “Memory System Programming.”
should be set to reflect the exact capabilities of the actual
SDRAM in the system.
The ‘enable internal PCI_CLK generator’ bit determines
the PCI_CLK pin operating mode. If this bit is ‘0’,
PCI_CLK acts compatible with TM-1000 and normal PCI
00 (100 MHz)
00
01 (75 MHz)
01
10 (50 MHz)
10
11 (33 MHz)
11
BOOT_CLK
bits
2
C speed as a function of EEPROM byte 0
0 (100 KHz)
1 (400 KHz)
0 (100 KHz)
1 (400 KHz)
0 (100 KHz)
1 (400 KHz)
0 (100 KHz)
1 (400 KHz)
EEPROM
speed bit
for more information on the
divider
value
1008
256
752
192
512
128
336
96
The boot value
99.2 KHz
390.6 KHz
99.7 KHz
390.6 KHz
97.6 KHz
390.6 KHz
98.2 KHz
343.8 KHz
actual I2C
speed
Section
operation, i.e. it is an input pin that takes PCI clock from
the external world. If this bit is ‘1’, an on-chip clock divider
in the XIO logic becomes the source of PCI_CLK, and
the PCI_CLK pin is configured as an output. In the latter
case, the PCI_CLK frequency can be programmed to a
divider of the PNX1300 highway clock by setting the
XIO_CTL register ‘Clock Frequency’ divider value. Refer
to
must be set if no external PCI clock is supplied.
The ‘SDRAM prefetchable’ bit is copied to the PCI con-
figuration space register DRAM_BASE and only visible
as bit #3 (P bit) of DRAM_BASE in a PCI configuration
read, but not visible by MMIO access. Its purpose is to
tell the PCI host, that SDRAM reads will cause no side ef-
fects. The host may apply optimizations on PCI access,
if this bit is set.
The ‘autonomous/host-assisted boot’ bit determines
whether the system boot logic will continue reading more
information from the EEPROM or halt its operation so the
host can complete system initialization. After the infor-
mation listed in
PNX1300 registers, an external PCI host processor can
finish the initialization of PNX1300. If no external PCI
host processor is present, the autonomous/host-assisted
boot bit should be set to ‘1’ to allow the system boot logic
to load the information described in the next section.
PRELIMINARY SPECIFICATION
Chapter 22, “PCI-XIO External I/O Bus.”
Table 13-2
has been loaded into
System Boot
Note: This bit
13-3