PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 296

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
22.7
The PCI-XIO Bus is a PCI target device. All valid PCI
transfers with PNX1300 as the initiator are allowed, in-
cluding single word and DMA transfers. When data is
read from the PCI-XIO Bus, it reads as a 32-bit word with
the 8 bits of data as the most significant byte and the 24-
bit XIO Bus transfer address as the least significant
bytes. When data is written to the PCI-XIO Bus, it is writ-
ten as a word, but only the most significant byte of the
data is transferred to the bus. The lower 24 bits are ig-
nored as they are replaced by the lower 24 bits of the
transfer address before being placed on the bus.
Before the PCI-XIO Bus can be used, the PCI-XIO Bus
Control Register must be set up. This register must be
loaded with the base address for the PCI-XIO bus and
the control fields for clock frequency, wait states per
transfer and PCI-XIO Bus enable.
To read a single byte to a PCI-XIO Bus device, first de-
fine the 24-bit address for the device. This might be the
address in an EPROM for the desired byte. Multiply this
device address by four to convert it to a word address
and add the XIO Bus base address. The combined ad-
dress is the PCI transfer address. Use this address as
the transfer address for a single word DSPCPU load.
Table 22-5
At the completion of the load, the data received will con-
sist of 8 bits of data and the 24-bit device address. To
write a byte, use the same transfer address and write a
word to this address with the desired data as the most
significant byte of the word written.
To transfer data between the XIO-PCI bus and the
SDRAM using the PCI DMA capability, set the
22-12
Figure 22-17. PCI-XIO Bus timing: DMA burst write, 2 bytes, 0 wait states
PCI_AD[31:24]: DATA
PCI_AD[23:0]: ADDR
PCI_C/BE1#/IOWR#
PCI_C/BE0#/IORD#
PCI_C/BE2#/DS#
PCI_INTB#/CE#
PCI_DEVSEL#
PCI-XIO BUS CONTROLLER
OPERATION AND PROGRAMMING
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
shows examples of this address conversion.
PCI_CLK
PRELIMINARY SPECIFICATION
Frame
PCI Com
PCI Addr
PCI Addr
PCI Com
PCI Com
data1
XIO Addrs 1
XIO Data 1
hold
data 2
Table 22-5. PCI to XIO Bus address conversion
examples
SRC_ADR or the DEST_ADR register to the PCI-XIO
Bus transfer address, depending on the direction of the
transfer. The PCI-XIO Bus transfer address is four times
the starting address as seen on the PCI-XIO Bus ad-
dress pins plus the PCI-XIO Bus controller base address.
This is the starting address for the PCI-XIO Bus transfer.
Set the other address, destination or source, to the de-
sired
PCI_DMA_CTL register for the desired direction and set
the transfer count to the four times number of PCI-XIO
Bus bytes to be transferred. The transfer count is four
times the PCI-XIO Bus bytes to be transferred because
the PCI-XIO Bus transfers one word to or from the PCI
bus for each byte transferred to or from devices on the
PCI-XIO Bus.
Word transfer is used to transfer the bytes to and from
the PCI bus for hardware simplicity. Additional hardware
could be added to pack and unpack bytes, but this is an
unnecessary complication given the speed of the PCI-
XIO Bus relative to the speed of the PNX1300 bus and
CPU. The primary intended use of the PCI-XIO Bus is for
ROMs, flash EPROMs and I/O devices. Because the
PCI-XIO bus is so much slower than the PNX1300, there
Address
XIO Bus
11 0012
in Hex
XIO Addrs 2
XIO Data 2
0123
11
starting
hold
PCI Word
Address
44 0048
in Hex
048C
address
bus idle
44
Philips Semiconductors
in
5800 0000
5800 0000
5800 0000
Address
XIO-PCI
in Hex
Base
SDRAM.
PCI Transfer
5800 048C
5800 0044
5844 0048
Address
in Hex
Set
the