XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 102

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

Functional Description
Voltage Compatibility
The 2.5V V
the user I/Os are separately powered by their respective
VCCO_# supplies.
When connecting the Spartan-3E JTAG port to a 3.3V inter-
face, the JTAG input pins must be current-limited to 10 mA
or less using series resistors. Similarly, the TDO pin is a
CMOS output powered from +2.5V. The TDO output can
directly drive a 3.3V input but with reduced noise immunity.
See XAPP453: The 3.3V Configuration of Spartan-3
FPGAs for additional information.
Table 67: Spartan-3E JTAG Device Identifiers
102
XC3S1200E
XC3S1600E
Spartan-3E
XC3S100E
XC3S250E
XC3S500E
TMS
TDO
TCK
TDI
FPGA
+2.5V
JTAG
CCAUX
JTAG
Mode
4-Bit Revision Code
supply powers the JTAG interface. All of
Step 0
P
‘1’
‘0’
‘1’
0x0
0x0
0x0
0x2
0x0
0x1
0x0
0x1
HSWAP
M2
M1
M0
TDI
PROG_B
TMS
TCK
Step 1
0x1
0x1
0x4
0x2
0x2
Spartan-3E
VCCINT
FPGA
+1.2V
GND
VCCAUX
Figure 65: JTAG Configuration Mode
Vendor/Device
VCCO_0
VCCO_2
0x1C 1A 093
0x1C 2E 093
0x1C 3A 093
0x1C 10 093
0x1C 22 093
DONE
Identifier
TDO
28-Bit
www.xilinx.com
VCCO_0
VCCO_2
+2.5V
JTAG Device ID
Each Spartan-3E FPGA array type has a 32-bit device-spe-
cific JTAG device identifier as shown in
28 bits represent the device vendor (Xilinx) and device iden-
tifer. The upper four bits, ignored by most tools, represent
the revision level of the silicon mounted on the printed circuit
board.
stepping level.
JTAG User ID
The Spartan-3E JTAG interface also provides the option to
store a 32-bit User ID, loaded during configuration. The
User ID value is specified via the UserID configuration bit-
stream option, shown in
Using JTAG Interface to Communicate to a
Configured FPGA Design
After the FPGA is configured, using any of the available
modes, the JTAG interface offers a possible communica-
tions
BSCAN_SPARTAN3 design primitive provides two private
JTAG instructions to create an internal boundary scan
chain.
JTAG
Mode
‘1’
‘0’
‘1’
P
Table 67
channel
HSWAP
M2
M1
M0
TDI
TMS
TCK
PROG_B
associates the revision code with a specific
to
Spartan-3E
VCCINT
+1.2V
GND
FPGA
Table 69, page
internal
VCCAUX
VCCO_0
VCCO_2
DS312-2 (v3.8) August 26, 2009
DONE
TDO
FPGA
Product Specification
Table
109.
VCCO_0
VCCO_2
+2.5V
67. The lower
DS312-2_56_082009
logic.
TMS
TCK
The
R