MPC8321VRADDC Freescale Semiconductor, MPC8321VRADDC Datasheet - Page 31

• Manufacturer Part Number: MPC8321VRADDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8321VRADDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 516
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 18
Figure 19
Figure 20
Freescale Semiconductor
At recommended operating conditions (see
JTAG external clock to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols used for timing specifications follow the pattern of t
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design and characterization.
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
inputs and t
timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
going to the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
provides the AC test load for TDO and the boundary-scan outputs of the MPC8323E.
provides the JTAG clock input timing diagram.
provides the TRST timing diagram.
(first two letters of functional block)(reference)(state)(signal)(state)
External Clock
Table 32. JTAG AC Timing Specifications (Independent of CLKIN)
TRST
Parameter
JTAG
Output
Figure 18. AC Test Load for the JTAG Interface
JTG
Boundary-scan data
Figure 19. JTAG Clock Input Timing Diagram
Table
VM
clock reference (K) going to the high (H) state. Note that, in general, the clock reference
t
JTKHKL
Figure 20. TRST Timing Diagram
2).
VM
VM = Midpoint Voltage (OV DD /2)
VM = Midpoint Voltage (OV DD /2)
TCLK
JTDXKH
Z
t
TCLK
JTG
0
TDO
= 50 Ω
.
VM
.
symbolizes JTAG timing (JT) with respect to the time data input signals
t
TRST
Symbol
t
t
JTKLOZ
JTKLDZ
(first two letters of functional block)(signal)(state)(reference)(state)
VM
for outputs. For example, t
2
R
L
VM
= 50 Ω
Min
TCLK
t
JTGR
2
2
to the midpoint of the signal in question.
OV
DD
JTDVKH
1
Max
t
(continued)
JTGF
/2
19
9
symbolizes JTAG device
JTG
clock reference (K)
Unit
Figure
ns
14).
Notes
5, 6
for
6
JTAG
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