MPC8321VRADDC Freescale Semiconductor, MPC8321VRADDC Datasheet - Page 70

• Manufacturer Part Number: MPC8321VRADDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8321VRADDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 516
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocking
22.6
The QUICC Engine PLL is controlled by the RCWL[CEPMF] and RCWL[CEPDF] parameters.
shows the multiplication factor encodings for the QUICC Engine PLL.
The RCWL[CEVCOD] denotes the QUICC Engine PLL VCO internal frequency as shown in
70
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
QUICC Engine PLL Configuration
The VCO divider (RCWL[CEVCOD]) must be set properly so that the
QUICC Engine VCO frequency is in the range of 300–600 MHz. The
QUICC Engine frequency is not restricted by the CSB and core frequencies.
The CSB, core, and QUICC Engine frequencies should be selected
according to the performance requirements.
The QUICC Engine VCO frequency is derived from the following
equations:
QUICC Engine VCO Frequency = ce_clk × VCO divider × (1 + CEPDF)
RCWL[CEPMF]
00000–00001
01001–11111
ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF)
00010
00011
00100
00101
00110
00111
01000
Table 61. QUICC Engine PLL Multiplication Factors
Table 62. QUICC Engine PLL VCO Divider
RCWL[CEVCOD]
RCWL[CEPDF]
00
01
10
11
0
0
0
0
0
0
0
0
0
NOTE
QUICC Engine PLL Multiplication
VCO Divider
Factor = RCWL[CEPMF]/
Reserved
(1 + RCWL[CEPDF)
4
8
2
Reserved
Reserved
× 2
× 3
× 4
× 5
× 6
× 7
× 8
Freescale Semiconductor
Table
Table 61
62.