MPC8321VRADDC Freescale Semiconductor, MPC8321VRADDC Datasheet - Page 76

• Manufacturer Part Number: MPC8321VRADDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8321VRADDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 516
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Design Information
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
where:
24 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8323E.
24.1
The MPC8323E includes three PLLs.
24.2
Each of the PLLs listed above is provided with power through independent power supply pins. The voltage
level at each AV
directly from V
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
76
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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
T
R
P
The system PLL (AV
The frequency ratio between the system and CLKIN is selected using the system PLL ratio
configuration bits as described in
The e300 core PLL (AV
ratio between the e300 core clock and the system clock is selected using the e300 PLL ratio
configuration bits as described in
The QUICC Engine PLL (AV
Engine block generates or uses external sources for all required serial interface clocks.
C
θ
D
System Clocking
PLL Power Supply Filtering
JC
= case temperature of the package (°C)
= power dissipation (W)
= junction-to-case thermal resistance (°C/W)
T
J
DD
DD
= T
through a low frequency filter scheme such as the following.
n pin should always be equivalent to V
C
+ (R
θ
JC
DD
× P
DD
2
)
generates the system clock from the externally supplied CLKIN input.
3
D
)
)
generates the core clock as a slave to the system clock. The frequency
DD
1
)
Section 22.4, “System PLL Configuration.”
Section 22.5, “Core PLL Configuration.”
which uses the same reference as the system PLL. The QUICC
Figure
DD
, and preferably these voltages are derived
44, one to each of the five AV
Freescale Semiconductor
DD
pins. By