MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 119

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

4.1 PRIVILEGE LEVELS
4.1.1 Supervisor Privilege Level
4-2
type of normal processing state, one without bus cycles. It is stopped, not
The processor operates at one of two levels of privilege: the user level or
the supervisor level. The supervisor level has higher privileges than the user
This allows a separation of supervisor and user so the supervisor can protect
system resources from uncontrolled access. The processor uses the privilege
supervisor privilege level and either the user stack pointer or a supervisor
stack pointer for stack operations. The processor identifies a bus access
tween supervisor and user can be maintained. The memory management
accesses to protect supervisor code, data, and resources from access by user
programs can access only their own code and data areas and can be restricted
from accessing other information. The operating system typically executes
at the supervisor privilege level. It has access to all resources, performs the
overhead tasks for the user level programs, and coordinates their activities.
The supervisor level is the higher privilege level. The privilege level is de-
termined by the S bit of the status register; if the S bit is set, the supervisor
to supervisor address spaces.
stack space associated with each user task and a separate stack space for
two is active. When the M bit is set to one, supervisor stack pointer references
cessor. (When the processor executes a STOP instruction, it is in a special
halted.)
level. Not all processor or coprocessor instructions are permitted to execute
in the lower privileged user level, but all are available at the supervisor level.
level indicated by the S bit in the status register to select either the user or
(supervisor or user mode) via the function codes so that differentiation be-
unit uses the indication of privilege level to control and translate memory
programs.
In many systems, the majority of programs execute at the user level. User
privilege level applies, and all instructions are executable. The bus cycles for
instructions executed at the supervisor level are normally classified as su-
pervisor references, and the values of the function codes on FC0-FC2 refer
In a multitasking operating system, it is more efficient to have a supervisor
interrupt associated tasks. The MC68030 provides two supervisor stacks,
master and interrupt; the M bit of the status register selects which of the
(either implicit or by specifying address register A7) access the master stack
MC68030 USER'S MANUAL
MOTOROLA