MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 32

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
1.1 FEATURES
The features of the MC68030 microprocessor are:
chip implementation of the MMU and the data and instruction caches. The
enhanced bus controller and the internal parallelism also provide increased
system performance. Finally, the improved bus interface, the reduction in
costs and satisfy cost/performance goals of the system designer.
Both improved performance and increased functionality result from the on-
physical size, and the lower power consumption combine to reduce system
• Object Code Compatible with the MC68020 and Earlier M68000 Micro-
• Complete 32-Bit Nonmultiplexed Address and Data Buses
•
• Two 32-Bit Supervisor Stack Pointers and 10 Special-Purpose Control
• 256-Byte Instruction Cache and 256-Byte Data Cache Can Be Accessed
• Paged MMU that Translates Addresses in Parallel with Instruction Exe-
• Two Transparent Segments Allow Untranslated Access to Physical Mem-
• Pipelined Architecture with Increased Parallelism Allows Accesses to
• Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks
• Dynamic Bus Sizing Supports 8-, 16-, 32-Bit Memories and Peripherals
• Support for Coprocessors with the M68000 Coprocessor Interface-- e.g.,
• 4-Gbyte Logical and Physical Addressing Range
• Implemented in Motorola's HCMQS Technology That Allows CMQS and
• Processor Speeds Beyond 20 MHz
tween Predefined Physical Addresses - - e.g., Graphics Applications
cution and Internal Cache Accesses
ory To Be Defined for Systems That Transfer Large Blocks of Data be-
minimum), Synchronous Bus Cycles (two clocks minimum), and Burst
Data Transfers (one clock minimum) all to the Physical Address Space
processors
Registers
Simultaneously
Internal Caches To Occur in Parallel with Bus Transfers and Instruction
Execution To Be Overlapped
Full IEEE Floating-Point Support Provided by the MC68881/MC68882
Floating-Point Coprocessors
HMOS (High-Density NMOS) Gates to be Combined for Maximum Speed,
Low Power, and Optimum Die Size
16 32-Bit General-Purpose Data and Address Registers
MC68030 USER'S MANUAL
1-3