MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 192

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
7.3.1
State 0
tempts to read two bytes at once, and for a byte operation, one byte. For
which each byte is read depends on the operand size, address signals (A0-A1),
Cache
erands, and cache interactions.
7-20 is a flowchart of a byte read cycle. The following figures show functional
corresponds to byte and word read cycles from a 32-bit port. Figure 7-22
corresponds to a long-word read cycle from an 8-bit port. Figure 7-23 also
applies to a long-word read cycle, but from a 16-bit port.
to the bus operation and are different from the processor states described
tions and timing diagrams of data transfer cycles are independent of the
or peripheral device. If the instruction specifies a long-word operation, the
some operations, the processor requests a three-byte transfer. The processor
properly positions each byte internally. The section of the data bus from
ClIN and CLOUT, whether the internal caches are enabled, and the port size.
Refer to 7.2.1
Figure 7-19 is a flowchart of an asynchronous long-word read cycle. Figure
read cycle timing diagrams specified in terms of clock periods. Figure 7-21
clock frequency. Bus operations are described in terms of external bus states.
During a read cycle, the processor receives data from a memory, coprocessor,
MC68030 attempts to read four bytes at once. For a word operation, it at-
Each of the bus cycles is defined as a succession of states. These states apply
in SECTION 4 PROCESSING STATES. The clock cycles used in the descrip-
Asynchronous Read Cycle
A0-A31 and valid function codes on FC0-FC2. The function codes select
the address space for the cycle. The processor drives R/W high for a read
come valid, indicating the number of bytes requested to be transferred.
The read cycle starts in state 0 (SO). The processor drives ECS low, indi-
cating the beginning of an external cycle. When the cycle is the first external
cycle of a read operand operation, operand cycle start (OCS) is driven low
at the same time. During SO, the processor places a valid address on
cycle and drives DBEI~ inactive to disable the data buffers. SIZ0-SIZ1 be-
CLOUT also becomes valid, indicating the state of the MMU CI bit in the
address translation descriptor or in the appropriate TTx register.
Filling for more information on dynamic bus sizing, misaligned op-
Dynamic Bus Sizing, 7.2.2 Misaligned Operands,
MC68030 USER'S MANUAL
and 7.2.6
7-31