MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 394

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
Address signals A16-A19 specify the CPU space cycle type for a CPU space
The MC68030 accesses the registers in the CIR set using standard asynchron-
ous or synchronous bus cycles. Thus, the bus interface implemented by a
coprocessor for its interface register set must satisfy the MC68030 address,
data, and control signal timing. The MC68030 timing information for read
and write cycles is illustrated in Figures 13-5-13-8 on foldout pages in the
operation is described in detail in SECTION 7 BUS OPERATION.
outputs high (FC2:FC0= 111)identifying a CPU space bus cycle. The CIR set
cessor access is used to generate the chip select signal for the coprocessor
The information encoded on the function code and address lines of the
are interrupt acknowledge, breakpoint acknowledge, and coprocessor access
cycles. CPU space type $2 (A19:A16=0010) specifies a coprocessor access
cycle.
Signals A13-A15 of the MC68030 address bus specify the coprocessor iden-
tification code CplD for the coprocessor being accessed. This code is trans-
ferred from bits 9-11 of the coprocessor instruction operation word (refer to
back of this manual. The MC68030 never requests a burst operation during
a coprocessor (CPU space) bus cycle, nor does it internally cache data read
or written during coprocessor (CPU space) bus cycles. The MC68030 bus
During coprocessor instruction execution, the MC68030 executes CPU space
bus cycles to access the CIR set. The MC68030 drives the three function code
is mapped into CPU space in the same manner that a peripheral interface
register set is generally mapped into data space. The information encoded
on the function code lines and address bus of the MC68030 during a copro-
being accessed. Other address lines select a register within the interface set.
MC68030 during a coprocessor access is illustrated in Figure 10-3.
bus cycle. The types of CPU space cycles currently defined for the MC68030
Figure 10-1) to the address bus during each coprocessor access. Thus, de-
FUNCTION
2
CODE
0
J
Figure 10-3. MC68030 CPU Space Address Encodings
0 0 0 0 0 0 0 O 0 0
MC68030 USER'S MANUAL
00100,01
[ _ _ 1
19
CPU SPACE
TYPE FIELD
T
ADDRESS BUS
15
c0,0 i0 0 0 0 0 D 0 01C'"RE0'S'ER
12
4
0
10-7
I
1(