MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 133

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

5
5.8 INTERRUPT CONTROL SIGNALS
5.8.1 Interrupt Priority Level Signals
5,8.2 Interrupt Pending (IPEND)
5.8.3 Autovector (AVEC)
5.9 BUS ARBITRATION CONTROL SIGNALS
5.9.1 BUS Request (BR)
5-8
the IPLn signals are active low, IPL0-1PL2 equal to $5 corresponds to an
This output signal indicates that an interrupt request has been recognized
This input signal indicates that the MC68030 should generate an automatic
vector during an interrupt acknowledge cycle. Refer to 7.4.1.2 AUTOVECTOR
vectors.
The following signals are the interrupt control signals for the MC68030.
These input signals provide an indication of an interrupt condition and the
encoding of the interrupt level from a peripheral or external prioritizing cir-
cuitry. IPL2 is the most
information on MC68030 interrupts.
(SR). This output is for use by external devices (coprocessors and other bus
masters, for example) to predict processor operation on the following in-
struction boundaries. Refer to 8.1.9
INTERRUPT ACKNOWLEDGE CYCLE for more information about automatic
The following signals are the three bus arbitration control signals used to
determine which device in a system is the bus master.
This input signal indicates that an external device needs to become the bus
structed from
interrupt request at interrupt level 2. Refer to 8.1.9
internally and exceeds the current interrupt priority mask inthe status register
mation. Also, refer to 7.4.1
information related to interrupts.
more information.
master. This is typically a "wire-ORed" input (but does not need to be con-
open-collector
significant
MC68030 USER'S MANUAL
devices). Refer to 7.7 BUS ARBITRATION for
Interrupt Acknowledge Bus Cycles
bit of the level number. For example, since
Interrupt Exceptions
Interrupt Exceptions
for interrupt infor-
MOTOROLA
for bus
for