MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 532

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
that accesses to the FPCP occur without unnecessary wait states. A PAL 16L8
this design is used. Should worst case conditions cause tCL K low to AS low
for this interface, Refer to MC68881UM/AD,
jectives:
Even though requirement (1) is not met under worst__case conditions, if the
CS generation circuit to meet requirement (2) provides the highest probability
according to the equations in Fig___ure 12-4, can be used to generate CS. For
a 25-MHz system, tCL K low to CS low is less than or equal to 10 ns when
to exceed requirement (1), one wait state is inserted in the access to the
The major concern of a system designer is to design a CS interface that meets
the AC electrical specifications for both the MC68030 (MPU) and the MC68881/
The following maximum specifications (relative to CLK low) meet these ob-
MPU AS is loaded within specifications and the AS input to the FPCP is
unbuffered, the requirement is met under typical conditions. Designing the
(see Figure 12-3) with a maximum propagation delay of 10 ns, programmed
FPCP; no other adverse effect occurs. Figure 12-5 shows the bus cycle timing
Coprocessor User's Manua/,
The circuit that generates CS must meet another requirement. When a non-
floating-point access immediately follows a float__iing-point__ access, CS (for the
floating-point access) must be negated before AS and DS (for the subsequent
ten signals (FC0-FC2 and A13-A19) provided by the PAL equations in Figure
tween multiple coprocessors in a system. Motorola assemblers always de-
fault to a CplD of $1 for floating-point instructions; this can be controlled
with assembler directives if a different CplD is desired or if multiple copro-
MC68882 (FPCP) without adding unnecessary wait states to FPCP accesses.
access) are asserted. The PAL circuit previously described also meets this
and A16-A17, FC0-FC1 indicate when a bus cycle is operating in either CPU
space ($7) or user-defined space ($3), and A16-A17 encode CPU space type
as coprocessor space ($2). A13-A15 can be ignored in this case because they
encode the coprocessor identification code (CplD) used to differentiate be-
cessors exist in the system.
requirement.
For example, if a system has only one coprocessor, the full decoding of the
12-4 is not absolutely necessary. It may be sufficient to use only FC0-FC1
tCL K low to CS Iow~<(MPU Spec 1 - M P U Spec 47A-FPCP Spec 19)
tCL K low to AS Iow~<(MPU Spec 1 - M P U Spec 47A-FPCP Spec 19)
MC68030 USER'S MANUAL
for FPCP specifications.
MC68881/MC68882 Floating-Point
12-7
(2)
(1)
12