MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 369

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

9.9.3.1 NUMBER OF TABLE LEVELS. The MMU supports from zero to five levels
9-68
9.9.3 Impact of M M U Features on Table Definition
tree with 32K-byte pages may be the best choice for systems that are primarily
features can affect the mapping decision and should be considered when
zero-level case is early termination at the root pointer. This provides a limit
of virtual memory space can use single-level tables. A single-level translation
At another extreme is a single-user business system that only needs a
system, because the block size formats of many Winchester hard disk file
systems is 512 bytes. A page table that completely maps the 2-Mbyte space
the one described in the preceding paragraph are small enough to be per-
A two-level address translation table provides a lower page level similar to
the page tables in the two preceding paragraphs and additional direction at
format descriptors, requiring 1K bytes for the table. Each of the upper table
of addresses. Virtual machine implementations require maximum availability
of virtual space. The disadvantages are the more complex table management
and the more restrictive accesses to other address spaces.
The features of the MMU that impact table definition are usually considered
after deciding how to map memory for the tasks. For some systems, these
making that decision.
(six levels with the use of indirection) in the address translation tables. The
check on the range of physical addresses for the system. It is used primarily
in systems that require the limit check on physical addresses.
Systems that support large page sizes or that require only limited amounts
numerically intensive (i.e., the system is involved in arithmetic manipulations
rather than data movement) where the overhead of virtual page faults and
paging I/O must be minimized. This type of system can map a 16-Mbyte
address space with only 2K bytes of page table space. With this much mapped
address space, table search time becomes insignificant.
2-Mbyte virtual address space. A 512-byte page size might be best for this
requires only 16K bytes of memory, and the ATC entries directly map 11K
bytes of virtual space at any one time. The page tables for this system and
manently allocated in the operating system data area. They incur virtually
no management or swapping overhead.
a higher level. For example, in a system using 32K-byte pages and 512-entry
page tables, the upper level translation table contains 256 entries of short-
MC68030 USER'S MANUAL
MOTOROLA