MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 176

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
transferred. The slave device latches the byte and acknowledges the data
transfer, indicating that the port is 16 bits wide. When the processor starts
the second cycle, the size signals specify that three bytes remain to be trans-
data items should be aligned on their natural boundaries. All instruction
words and extension words must reside on word boundaries. Attempting to
exception.
word-organized memory, which requires three bus cycles. For the first cycle,
the size signals specify a long-word transfer, and the address offset (A2:A0)
ferred with an address offset (A2:A0) of 010. The next two bytes are trans-
ferred during this cycle. The processor then initiates the third cycle, with the
size signals indicating one byte remaining to be transferred. The address
offset (A2:A0) is now 100; the port latches the final byte; and the operation
organized memory. This example is similar to the one shown in Figures 7-9
and 7-10 except that the operand is word sized and the transfer requires only
two bus cycles.
long-word or word operands that are misaligned. For maximum performance,
prefetch an instruction word at an odd address causes an address error
Figure 7-9 shows the transfer of a long-word operand to an odd address in
is 001. Since the port width is 16 bits, only the first byte of the long word is
is complete. Figure 7-10 shows the associated bus transfer signal timing.
Figure 7-1 1 shows the equivalent operation for a cachable data read cycle.
Figures 7-12 and 7-13 show a word transfer to an odd address in word-
Figure 7-14 shows the equivalent operation for a cachable data read cycle.
Figure 7-9. Misaligned Long-Word Transfer to Word Port Example
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MC68030 USER'S MANUAL
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7-15
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