MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 588

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Exception (Continued)
Exception Related
Exceptions,
Extended Instruction Timing Table, 11-43
F-Line, 10-4
FC0-FC2 Signals, 5-4, 6-6, 7-4, 7-31ff
FD Bit, 6-22
Fetch Effective Address Timing Table, 11-26
FI Bit, 6-23
Fields, Limit, 9-70
Execution Time Calculations, 11-5ff
Execution Unit, 6-16
External Cache, 12-30-12-35
External Cycle Start Signal, 5-5, 7-4, 7-26
Fault, Double Bus, 7-94, 8-7
Fetch Immediate Effective Address Timing Table,
Floating Point Units, 12-5
Flowchart,
MOTOROLA
Privilege Violation, 8-11, 10-69
Processing, 4-6
Reset, 8-3, 8-4
Return from, 8-24
Stack Frame, 4-5, 8-32
Trace, 8-12, 10-70
Vector
Vectors, 4-6
Address Translation, General, 9-14
Asynchronous Byte Read Cycle, 7-32
Instruction Trap, 8-9
MMU Configuration, 8-21, 9-62
Priority, 8-16
Unimplemented Instruction, 8-9
Instruction Timing Table, 11-50
Operation Timing Table, 11-50
Bus, 7-75
Coprocessor Data Processing, 10-63
Coprocessor Detected, 10-62
Coprocessor System Related, 10-64
F-Line Emulator, 8-10, 10-68
Multiple, 8-23
Primitive Processing, 10-66
Emulator Exceptions, 8-10, 10-68
Asynchronous Long Word Read Cycle, 7-32
Asynchronous Read-Modify-Write Cycle, 7-44
Format Error, 8-14
Illegal Instruction, 8-9
Interrupt, 8-14, 10-71
Implementation, 12-30-12-35
Instruction Only, 12-35
11-30
Sequence, 8-1
State, 4-1
Assignments, 8-2
Numbers, 8-2
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MC68030 USER'S MANUAL
Flowchart (Continued)
Format,
Format Error Exception, 8-14
Format Errors,
Format Word,
Format Words, Coprocessor, 10-22
Formula, Instruction Cache Case Time, 11-I I - I 1-14
Freeze Data Cache Bit, 6-22
Freeze Instruction Cache Bit, 6-23
Function Code Lookup, 9-45, 9-46
Function Code Signals, 5-4, 6-6, 7-4, 7-31ff
General Description, 1-1
GetFrame Routine, 9-85
GND Pin Assignments, 12-46
Grant, Bus, 7-99
Ground Considerations, 12-43
Groups, Signal, 5-1
Halt _Signal, 5-9, 7-6, 7-27ff
HALT Signal, 5-9, 7-6, 7-27ff
Function Code Registers, I-8, 2-5
Halt Operation, 7-91
Halted State, 4-1
Coprocessor Instruction, 10-4
Coprocessor Response Primitive, 10-35
Asynchronous Write Cycle, 7-37
ATC Entry Creation, 9-42
Descriptor Fetch Operation, 9-44
interrupt Acknowledge Cycle, 7-71
Limit Check Procedure, 9-43
Synchronous Long-Word Read Cycle, 7-49
Synchronous Read-Modify-Write Cycle, 7-55
Instruction, 3-1
Instruction Description, 3-18
Coprocessor Detected, 10-61
Main Processor Detected, 10-65
Empty/Reset, 10-22
Invalid, 10-23
Valid, 10-24
Example, 9-46
Timing, 7-93
Breakpoint Acknowledge, 7-75
Burst Operation, 7-62
Bus Arbitration, 7-98
Not Ready, 10-23
Logical Address Map, 9-46
Table Search
Detailed, 9-41
Initialization, 9-42
Simplified, 9-29
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