MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 204

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.3.3 A s y n c h r o n o u s R e a d - M o d i f y - W r i t e Cycle
MOTOROLA
the contents of the data cache as described in 6.1.2. Data Cache.
The test and set (TAS) and compare and swap (CAS and CAS2) instructions
write cycle(s) may not occur. Table search accesses required for the MMU
these cycles, a write does not occur unless a descriptor is updated. No data
The read-modify-write cycle performs a read, conditionally modifies the data
sequence, the MC68030 asserts the RMC signal to indicate that an indivisible
operation is occurring. The MC68030 does not issue a bus grant (BG) signal
altered the value being read. However, read-modify-write cycles may alter
are the only MC68030 instructions that utilize read-modify-write operations.
are always read-modify-write cycles to the supervisor data space. During
addresses to access the tables. Refer to SECTION 9 MEMORY MANAGEMENT
eration. Figure 7-30 is an example of a functional timing diagram of a TAS
State 0
State 1
in the arithmetic logic unit, and may write the data out to memory. In the
MC68030 processor, this operation is indivisible, providing semaphore ca-
pabilities for multiprocessor systems. During the entire read-modify-write
in response to a bus request (BR) signal during this operation. The read
portion of a read-modify-write operation is forced to miss in the data cache
because the data in the cache would not be valid if another processor had
No burst filling of the data cache occurs during a read-modify-write operation.
Depending on the compare results of the CAS and CAS2 instructions, the
is internally cached for table search accesses since the MMU uses physical
UNIT for information about the MMU.
Figure 7-29 is a flowchart of the asynchronous read-modify-write cycle op-
instruction specified in terms of clock periods.
The processor asserts ECS and OCS in SO to indicate the beginning of an
external operand cycle. The processor also asserts RMC in SO to identify
a read-modify-write cycle. The processor places a valid address on A0-A31
and valid function codes on FC0-FC2. The function codes select the address
space for the operation. SIZ0-SIZ1 become valid in SO to indicate the
operand size. The processor drives R/W high for the read cycle and sets
CLOUT according to the value of the MMU CI bit in the address translation
descriptor or in the appropriate TTx register.
One-half clock later in $1, the processor asserts AS, indicating that the
address on the address bus is valid. The processor asserts DS during $1.
In addition, the ECS (and OCS, if asserted) signal is negated during $1.
MC68030 USER'S MANUAL
7-43
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