MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 412

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

10.2.3.3.2 Protocol.
MOTOROLA
The control alterable and predecrement addressing modes are valid for the
following the cpSAVE instruction operation word. These words contain any
the coprocessor.) The coprocessor communicates status information asso-
code in bits [0-5]. The effective address encoded in the cpSAVE instruction
of the coprocessor is saved in memory.
cpSAVE instruction. Other addressing modes cause the MC68030 tO initiate
LATOR EXCEPTIONS.
The instruction can include as many as five effective address extension words
additional information required to calculate the effective address specified
save instruction. The main processor initiates execution of the cpSAVE in-
struction by reading the save CIR. Thus, the cpSAVE instruction is the only
coprocessor instruction that begins by reading from a CIR. (All other copro-
cessor instructions write to a CIR to initiate execution of the instruction by
ciated with the context save operation to the main processor by placing
coprocessor format codes in the save CIR.
again. After placing the not ready format code in the save CIR, the coprocessor
should either suspend or complete the instruction it is currently executing.
ecuting, it places a format code representing the internalcoprocessor state
format word to the effective address specified in the cpSAVE instruction. The
state information, not including the format word and associated null word,
is the address at which the state frame associated with the current context
F-line emulator exception processing as described in 10.5.2.2 F-LINE EMU-
by bits [0-5] of the operation word.
If the coprocessor is not ready to suspend its current operation when the
main processor reads the save CIR, it returns a "not ready" format code. The
main processor services any pending interrupts and then reads the save CIR
Once the coprocessor has suspended or completed the instruction it is ex-
in the save CIR. When the main processor reads the save CIR, it transfers the
lower byte of the coprocessor format word specifies the number of bytes of
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Figure 10-15. Coprocessor Context Save Instruction Format (cpSAVE)
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Figurej10-16 shows the protocol for the coprocessor context
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i1 I
EFFECTIVE ADDRESS EXTENSION WORDS (0-5 WORDS)
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MC68030 USER'S MANUAL
cpio
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I 1 I o I o I
8
7
6
5
EFFECTIVE A00 ESS
10-25
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