PCA9665D,112 NXP Semiconductors, PCA9665D,112 Datasheet - Page 11

• Manufacturer Part Number: PCA9665D,112
• Description: IC CNTRLR PARALLEL/I2C 20-SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9665D,112

• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Supply: 100µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279242112; PCA9665D; PCA9665D

NXP Semiconductors
PCA9665_3
Product data sheet
7.3.1.5 The indirect data field access register, INDIRECT (A1 = 1, A0 = 0)
Table 12.
Remark: ENSIO bit value must be changed only when the I
The registers in the indirect address space can be accessed using the INDIRECT data
field. Before writing or reading such a register, the INDPTR register should be written with
the address of the indirect register that needs to be accessed. Once the INDPTR register
contains the appropriate value, reads and writes to the INDIRECT data field will actually
read and write the selected indirect register.
Bit
5
4
3
2:1
0
Symbol Description
STA
STO
SI
-
MODE
I2CCON - Control register (A1 = 1, A0 = 1) bit description
The START flag.
STA = 1: When the STA bit is set to enter a master mode, the bus controller
hardware checks the status of the I
bus is free. If the bus is not free, then the bus controller waits for a STOP condition
(which will free the bus) and generates a START condition after the minimum
buffer time (t
If STA is set while the bus controller is already in a master mode and one or more
bytes are transmitted or received, the bus controller transmits a repeated START
condition. STA may be set at any time. STA may also be set when the bus
controller is an addressed slave. A START condition will then be generated after a
STOP condition and the minimum buffer time (t
STA = 0: When the STA bit is reset, no START condition or repeated START
condition will be generated.
The STOP flag.
STO = 1: When the STO bit is set while the bus controller is in a master mode, a
STOP condition is transmitted on the I
on the bus, the hardware clears the STO flag.
If the STA and STO bits are both set and the PCA9665 is in master mode, then a
STOP condition is transmitted on the I
START condition after the minimum buffer time (t
STO = 0 : When the STO bit is reset, no STOP condition will be generated.
The Serial Interrupt flag.
SI = 1: When the SI flag is set, and, if the ENSIO bit is also set, a serial interrupt is
requested. SI is set by hardware when one of 29 of the 30 possible states of the
bus controller states is entered. The only state that does not cause SI to be set is
state F8h, which indicates that no relevant state information is available.
While SI is set, the LOW period of the serial clock on the SCL line is stretched,
and the serial transfer is suspended. A HIGH level on the SCL line is unaffected
by the serial interrupt flag. SI is automatically cleared when the I2CCON register
is written. The SI bit cannot be set by the user.
SI = 0: When the SI flag is reset, no serial interrupt is requested, and there is no
stretching of the serial clock on the SCL line.
Reserved. When I2CCON is read, zeroes are read. Must be written with zeroes.
The Mode flag.
MODE = 0; Byte mode. See
MODE = 1; buffered mode. See
Rev. 03 — 12 August 2008
BUF
) has elapsed.
Section 8.1.1 “Byte mode”
Section 8.1.2 “Buffered mode”
2
C-bus and generates a START condition if the
2
Fm+ parallel bus to I
2
C-bus. When a STOP condition is detected
C-bus. The bus controller then transmits a
BUF
BUF
2
) has elapsed.
C-bus is idle.
) has elapsed.
…continued
for more detail.
PCA9665
© NXP B.V. 2008. All rights reserved.
2
C-bus controller
for more detail.
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