PCA9665D,112 NXP Semiconductors, PCA9665D,112 Datasheet - Page 61

• Manufacturer Part Number: PCA9665D,112
• Description: IC CNTRLR PARALLEL/I2C 20-SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9665D,112

• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Supply: 100µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279242112; PCA9665D; PCA9665D

NXP Semiconductors
PCA9665_3
Product data sheet
Fig 18. Parallel Software Reset sequence
internal
D[7:0]
A[1:0]
signal
reset
WR
8.11 Reset
Indirect Register pointer
I2CPRESET register selected
Reset of the PCA9665 to its default state can be performed in 2 different ways:
The RESET hardware pin and software reset function only resets the internal registers
and control logic, and does not re-initialize the internal oscillator because the oscillator
initialization is performed only on power-up. If the device hangs up and does not respond
to a normal RESET input or software reset command, the only way to recover is by
powering down and then powering the device back up.
A simple way to implement this circuit without actually having to de-power the entire
system is by using a dual gate buffer such as the 74LVC2G125 to control the V
PCA9665 as shown in
directly from the supply rail, it is powered by the output of the 74LVC2G125 with its input
connected to the supply rail. Ganging up the two buffers provides twice the drive and
minimizes the voltage drop. The 74LVC2G125 enable pins (1OE, 2OE) are now used to
power cycle and recover the PCA9665.
A 100 pF capacitor is used for filtering the supply of PCA9665 and averaging the dynamic
current (typically, maximum peak current is 24 mA). Do not size the capacitor too large as
the larger capacitor could discharge during power-down, and possibly damage the output
of the buffer.
The enable pins are pulled down to ground by a 10 k resistor. During normal operation,
the enable pins are held LOW and the buffer is turned on, powering the PCA9665. An
external signal (either from a controller or processor) controls the 74LVC2G125 enable
pins to switch on or switch off the supply voltage of the PCA9665. A HIGH logic level
places the buffer in a high-impedance state and turns off the supply to the PCA9665,
which discharges through the 100 pF capacitor. When the enable pins are once again
pulled LOW, the PCA9665 powers up and re-initializes to an operation state.
access to INDPTR
•
•
By holding the RESET pin LOW for a minimum of t
By using the Parallel Software Reset sequence as described in
00
following byte is ignored
05h
and reset is aborted.
If D[7:0]
A5h,
Rev. 03 — 12 August 2008
Figure
SWRST data byte 1
SWRST Data 2 = 5Ah, PCA9665
If D[7:0]
19. Now, instead of powering the V
If SWRST Data 1 = A5h and
A5h
is reset to its default state.
access to the INDIRECT
5Ah, reset is aborted.
Indirect Data field
10
Fm+ parallel bus to I
SWRST data byte 2
w(rst)
5Ah
.
DD
Figure
of the PCA9665
PCA9665
© NXP B.V. 2008. All rights reserved.
2
C-bus controller
18.
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DD
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