PCA9665D,112 NXP Semiconductors, PCA9665D,112 Datasheet - Page 45

• Manufacturer Part Number: PCA9665D,112
• Description: IC CNTRLR PARALLEL/I2C 20-SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9665D,112

• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Supply: 100µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279242112; PCA9665D; PCA9665D

NXP Semiconductors
PCA9665_3
Product data sheet
Fig 14. Format and states in the Slave Transmitter Buffered mode (MODE = 1)
reception of own
slave address and
transmission of one
or more data bytes
arbitration lost as MST and
addressed as slave
(1) See
(2) Defined state when the number of bytes sent is equal to the value in I2CCOUNT register.
(3) Defined state when a NACK is received. The number of bytes transmitted is lower than or equal to the value in the I2CCOUNT
(4) Defined state after the last byte has been transmitted and the PCA9665 goes to the non-addressed mode (AA = 0) and an ACK
DATA
register.
is received. The number of bytes that are transmitted is equal to the value in I2CCOUNT register.
from master to slave
from slave to master
Table
8.4.4 Slave Transmitter Buffered mode
31.
n
A
In the Slave Transmitter Buffered mode, a number of data bytes are transmitted to a
master receiver several bytes at a time (see
Slave Receiver Buffered mode. When I2CADR and I2CCON have been initialized, the
PCA9665 waits until it is addressed by its own slave address followed by the data direction
bit which must be ‘1’ (R) for the PCA9665 to operate in the Slave Transmitter mode. After
its own slave address and the R bit have been received, the Serial Interrupt flag (SI) is set,
the Interrupt line (INT) goes LOW and I2CSTA is loaded with A8h. This status code is
used to vector to an interrupt service routine, and the appropriate action to be taken is
detailed in
The Slave Transmitter Buffered mode may also be entered if arbitration is lost while the
PCA9665 is in the master mode. See state B0h and appropriate actions in
The byte count register (I2CCOUNT) is programmed with the number of bytes that need
to be sent in a single sequence (BC[6:0]) as shown in
Receiver Buffered modes and can be programmed to either logic 0 or logic 1.
If the AA bit is reset during a transfer, the PCA9665 will transmit all the bytes of the
transfer (values defined by BC[6:0]) and enter state C8h. The PCA9665 is switched to the
not addressed slave mode and will ignore the master receiver if it continues the transfer.
Thus the master receiver receives all ‘1’s as serial data. While AA is reset, the PCA9665
does not respond to its own slave address. However, the I
address recognition may be resumed at any time by setting AA. This means that the AA
bit may be used to temporarily isolate the PCA9665 from the I
any number of data bytes and
their associated Acknowledge bits
This number (contained in I2CSTA) corresponds
to a defined state of the I
S
SLA
Table
R
41.
2
C-bus.
A8h
B0h
Rev. 03 — 12 August 2008
A
A
(1)
DATA
last data byte transmitted;
switched to Not Addressed slave
(AA bit in I2CCON = 0)
B8h
(2)
A
Figure
Fm+ parallel bus to I
DATA
14). Data transfer is initialized as in the
Table
2
C0h
C8h
C-bus is still monitored, and
(3)
(4)
A
A
39. LB bit is only used for the
2
on STOP
C-bus.
P or S
F8h
ALL '1's
PCA9665
© NXP B.V. 2008. All rights reserved.
2
C-bus controller
Table
002aab662
on STOP
P or S
F8h
41.
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