PCA9665D,112 NXP Semiconductors, PCA9665D,112 Datasheet - Page 5

• Manufacturer Part Number: PCA9665D,112
• Description: IC CNTRLR PARALLEL/I2C 20-SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9665D,112

• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Supply: 100µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279242112; PCA9665D; PCA9665D

NXP Semiconductors
PCA9665_3
Product data sheet
6.2 Pin description
Table 2.
[1]
Symbol Pin
D0
D1
D2
D3
D4
D5
D6
D7
i.c.
V
WR
RD
CE
A0
A1
INT
RESET
SCL
SDA
V
SS
DD
HVQFN20 package die supply ground is connected to both the V
V
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
SS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
DIP20,
SO20,
TSSOP20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin description
HVQFN20
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Rev. 03 — 12 August 2008
[1]
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
power
I
I
I
I
I
O
I
I/O
I/O
power
Description
Data bus: Bidirectional 3-state data bus used to
transfer commands, data and status between the bus
controller and the CPU. D0 is the least significant bit.
internally connected: must be left floating (pulled
LOW internally)
Supply ground
Write strobe: When LOW and CE is also LOW, the
content of the data bus is loaded into the addressed
register. Data are latched on the rising edge of either
WR or CE.
Read strobe: When LOW and CE is also LOW,
causes the contents of the addressed register to be
presented on the data bus. The read cycle begins on
the falling edge of RD.
Chip Enable: Active LOW input signal. When LOW,
data transfers between the CPU and the bus
controller are enabled on D0 to D7 as controlled by
the WR, RD and A0 to A1 inputs. When HIGH,
places the D0 to D7 lines in the 3-state condition.
Data are written into the addressed register on rising
edge of either CE or WR.
Address inputs: Selects the bus controller’s internal
registers and ports for read/write operations.
Interrupt request: Active LOW, open-drain, output.
This pin requires a pull-up device.
Reset: Active LOW input. A LOW level clears internal
registers and resets the I
I
This pin requires a pull-up device.
I
requires a pull-up device.
Power supply: 2.3 V to 3.6 V
2
2
C-bus serial clock input/output (open-drain).
C-bus serial data input/output (open-drain). This pin
Fm+ parallel bus to I
SS
pin and the exposed center pad. The
2
C-bus state machine.
PCA9665
© NXP B.V. 2008. All rights reserved.
2
C-bus controller
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