PCA9665D,112 NXP Semiconductors, PCA9665D,112 Datasheet - Page 13

• Manufacturer Part Number: PCA9665D,112
• Description: IC CNTRLR PARALLEL/I2C 20-SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9665D,112

• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Supply: 100µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279242112; PCA9665D; PCA9665D

NXP Semiconductors
PCA9665_3
Product data sheet
7.3.2.3 The Clock Rate registers, I2CSCLL and I2CSCLH (indirect addresses 02h and 03h)
I2CSCLL and I2CSCLH are 8-bit read/write registers. They define the data rate for the
PCA9665 when used as a bus master. The actual frequency is determined by t
where SCL is HIGH), t
t
and I2CSCLL registers and the internal oscillator frequency. t
system/application dependent.
with T
Remark: The I2CMODE register needs to be programmed before programming the
I2CSCLL and I2CSCLH registers in order to know which I
Section 7.3.2.6 “The I
detail.
Standard-mode is the default selected mode at power-up or after reset.
Table 17.
Table 18.
Table 19.
Table 20.
Bit
7:0
Bit
7:0
HIGH
f
SCL
H7
L7
7
7
and t
=
osc
---------------------------------------------------------------------------------------------- -
T
= internal oscillator period = 35 ns
osc
LOW
Symbol
L[7:0]
Symbol
H[7:0]
I2CSCLL - Clock Rate Low register (indirect address 02h) bit allocation
I2CSCLL - Clock Rate Low register (indirect address 02h) bit description
I2CSCLH - Clock Rate High register (indirect address 03h) bit allocation
I2CSCLH - Clock Rate High register (indirect address 03h) bit description
I 2CSCLL
are calculated based on the values that are programmed into I2CSCLH
H6
L6
6
6
2
LOW
Rev. 03 — 12 August 2008
C-bus mode register, I2CMODE (indirect address 06h)”
+
I 2CSCLH
Description
Eight bits defining the LOW state of SCL.
Description
Eight bits defining the HIGH state of SCL.
1
H5
L5
(time where SCL is LOW), t
5
5
+
H4
L4
4
4
t
r
+
t
f
5 ns
H3
L3
Fm+ parallel bus to I
3
3
r
(rise time), and t
2
C-bus mode is selected. See
H2
L2
2
2
r
and t
f
are
PCA9665
© NXP B.V. 2008. All rights reserved.
2
H1
L1
f
1
1
C-bus controller
(fall time) values.
for more
HIGH
H0
L0
13 of 90
0
0
(time
(1)