PCA9665D,112 NXP Semiconductors, PCA9665D,112 Datasheet - Page 50

• Manufacturer Part Number: PCA9665D,112
• Description: IC CNTRLR PARALLEL/I2C 20-SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9665D,112

• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Supply: 100µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279242112; PCA9665D; PCA9665D

NXP Semiconductors
PCA9665_3
Product data sheet
8.5.4 Buffered Slave Receiver mode
8.5.5 Example: Read 128 bytes in two 64-byte sequences of an EEPROM
(I
starting at Location 08h
6. More sequences (program I2CCOUNT register, load data bytes in I2CDAT buffer,
1. An interrupt is asserted and the SI bit is set in the I2CCON register when the
2. Program the I2CCOUNT register with the number of bytes that needs to be read from
3. The I2CCON is programmed to clear the previous Interrupt. The PCA9665 receives
4. When the sequence has been executed (BC[6:0] bytes have been received or the
5. More sequence (program the I2CCOUNT register, write to the I2CCON register, read
1. Program I2CCOUNT = 02h (2 bytes to be sent): I
2. Write A0h (I
3. Program I2CCON with STA = 1, STO = SI = 0, MODE = 1.
4. Program I2CCON with STA = STO = SI = 0, MODE = 1.
2
C-bus address = A0h for write operations and A1h for read operations)
write the I2CCON register to send the data to the I
when sequence has been executed) can be performed as long as the master
acknowledges the bytes sent by the PCA9665 and AA = 1. Slave Transmitter Buffered
mode ends when the I
PCA9665 goes to Non-addressed Slave mode.
PCA9665‘s own slave address has been detected in the I
address defined in the I2CADR register). In Slave Receiver mode, R/W = 0.
a master device in the I
Receiver mode to let the PCA9665 know if the last byte received must be
acknowledged or not.
LB = 0: Last received byte is acknowledged and another sequence can be executed.
LB = 1: Last received byte is not acknowledged.
data from the I
I2CCON register is performed.
master sent a STOP or Repeated START command), an Interrupt is asserted and the
SI bit is set in the I2CCON register. The I2CSTA register contains the status of the
transmission and the I2CCOUNT register contains the number of bytes that have
been received. I2CDAT buffer contains all the data that has been received and can be
read by the microcontroller.
the I2CDAT buffer) can be performed as long as a STOP or a Repeated START
command has not been sent by the I
ends when the I
when the PCA9665 does not acknowledge the received bytes any more.
allocation.
I2CDAT register.
– the PCA9665 sends a START command
– the PCA9665 sends an interrupt, sets SI = 1 and updates I2CSTA register
– I2CSTA reads 08h
– I
2
C-bus slave address A0h, then EEPROM sub address 08h is sent on the bus
2
C-bus slave address and write command) and 08h (Location) into the
2
C-bus master. MODE bit must be set to ‘1’ each time a write to the
2
C-bus master sends a STOP or Repeated START command, or
Rev. 03 — 12 August 2008
2
2
C-bus master does not acknowledge a byte or when the
C-bus (BC[6:0] has a value from 01h to 44h). LB bit is used in
2
C-bus master. Slave Receiver Buffered mode
Fm+ parallel bus to I
2
C-bus slave address and memory
2
C-bus, read the I2CSTA register
2
C-bus (AA = 1, own slave
PCA9665
© NXP B.V. 2008. All rights reserved.
2
C-bus controller
50 of 90