T7115AMCD LSI, T7115AMCD Datasheet - Page 22

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
Bit 7 of the SF status byte is the CRC status bit. If an
incorrect CRC was detected, this bit is set to 1. If the
CRC was correct, the bit is 0.
Bit 6 of the SF status byte is the abort status. A high (1)
indicates the frame associated with this status byte was
aborted (i.e., the abort sequence was detected after an
opening flag and before a subsequent closing flag). An
abort can also cause bits 7 and/or 4 to go high (1). An
abort is not reported when a flag is followed by seven
1s.
If the Overrun bit (bit 5) is high, it indicates that a
receiver FIFO overrun occurred (the 64-byte FIFO size
was exceeded; see the Receiver Overrun section).
The Bad Byte Count bit (Bit 4) indicates whether or not
the bit count received was a multiple of eight (i.e., an
integer number of bytes). A high (1) indicates that the
bit count received after 0-bit deletion was not a multiple
of eight, and a low indicates that the bit count was a
multiple of eight. When a non-byte-aligned frame is
received, all bits received are present in the receive
FIFO. The byte before the SF status byte contains less
than eight valid data bits. The nondata bits are the first
bits of the received CRC. The T7121 provides no indi-
cation of how many of the bits in the byte are valid. It is
up to the user and the protocol to decide what to do
with non-byte-aligned frames.
Bits 0 to 3 of the SF status byte are not used and are
guaranteed to be 0 when read. A good frame is implied
when the SF status byte is 00 hexadecimal.
The last byte of a completed frame in the receive FIFO
is always the SF status byte. As a frame is received,
the two bytes preceding the closing flag are assumed
to be the frame check sequence (CRC) bits and are not
loaded into the receiver FIFO. Thus, the final 2 bytes
received in an aborted frame are not placed in the
queue, and an aborted frame of 2 bytes or less causes
only an SF status byte to appear in the receiver FIFO.
The writing of the SF status byte is followed by the
REOF (R15—B4) interrupt bit being set. The REOF
event triggers an interrupt, unless the interrupt is
masked by REOFIE (R14—B4) = 0, whenever no other
unmasked interrupts are active.
22
22
(continued)
The Receive Queue Status bits (RQS, R4—[6—0]) are
updated as bytes are loaded into the receive FIFO. The
SF status byte is included in the byte count. When the
first SF status byte is placed in the FIFO, the EOF
(R4—B7) bit is set, and the status freezes until the
FIFO is read. As bytes are read from the FIFO, the sta-
tus decreases until it reads 1. The byte read when the
RQS is "0000001" and the EOF bit is high (1) is the SF
status byte describing the error status of the frame just
read. Once the first SF status byte is read from the
FIFO, the FIFO status is updated to report the number
of bytes to the next SF status byte, if any, or the number
of additional bytes present. When EOF (R4—B7) is
low, no SF status byte is currently present in the FIFO,
and the RQS bits report the number of bytes present.
As bytes are read from the FIFO, the status decreases
with each read until it reads 0 when the FIFO is totally
empty. The EOF bit is also low when the FIFO is com-
pletely empty. Thus, the RQS and EOF bits provide a
mechanism to recognize the end of one frame and the
beginning of another. Reading the receiver status reg-
ister (R4) does not affect the FIFO buffers. In the event
of a receiver overrun (see below), an SF status byte is
written to the receive FIFO. Multiple SF status bytes
can be present in the FIFO. Remember, the RQS
reports only the number of bytes to the first SF status
byte.
To allow users to tailor receiver FIFO service intervals
to their systems, the Receiver Interrupt Level bits
(RIL, R5—B[5—0]) are provided. These bits are coded
in binary and determine when the Receiver Full
(RF, R15—B3) interrupt is asserted. The interrupt pin
transition can be masked by clearing RFIE, R14—B3 to
0. The value programmed in the RIL bits equals the
total number of bytes necessary to be present in the
FIFO to trigger an RF interrupt. The RF interrupt alone
is not sufficient to determine the number of bytes to
read as some of the bytes may be SF status bytes. The
RQS bits and EOF bit in register 4 allow the user to
determine the number of bytes to read. The REOF
interrupt can be the only interrupt for the final frame of
a group of frames, since the number of bytes received
to the end of the frame cannot be sufficient to trigger an
RF interrupt.
Lucent Technologies Inc.
Data Sheet
April 1997