T7115AMCD LSI, T7115AMCD Datasheet - Page 39

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Data Sheet
April 1997
Lucent Technologies Inc.
Functional Description
Table 18. Register R11—Receiver Time-Slot Offset Control Register
Register
R11—B7
R11
R11
R11
DRI
(0)
B(0—5)
R11—B6
Bit
B6
B7
RLBIT
(1)
RTSOF0—RTSOF5 Receiver Time-Slot Offset. The value of these 6 bits, coded in
R11—B5
RTSOF5
Symbol
(continued)
RLBIT
DRI
(0)
R11—B4
RTSOF4
binary with bit 0 being the LSB, specifies the number of time slots
to delay between the beginning of the first locatable TDM highway
time slot and the beginning of a new virtual TDM frame (i.e., the
time slot defined by the user as time slot 0.) See Figure 5 for an
example of using the RTSOF bits.
Receive Least Significant Bit First. This bit is used to control
whether the least significant or most significant data bit is
received first. The least significant data bit in the receive FIFO is
defined as that bit which is read on AD0 when the FIFO is read.
When RLBIT is 0, the most significant bit of data is received first,
and when RLBIT is set to 1, the least significant bit of data is
received first.
RLBIT has no meaning when not in the TDM highway mode (i.e.,
HWYEN, R0—B7 = 0). In non-TDM highway mode, data is
always received least significant bit first.
Receive Data Inverted. If this bit is set to 1, the serial data input
to the DRA (or DRB) pin is inverted before data is passed to the
HDLC receiver (or FIFO in the transparent mode).
(0)
R11—B3
RTSOF3
T7121 HDLC Interface for ISDN (HIFI-64)
(0)
Name/Function
R11—B2
RTSOF2
(0)
R11—B1
RTSOF1
(0)
R11—B0
RTSOF0
(0)
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