T7115AMCD LSI, T7115AMCD Datasheet - Page 34

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
Table 12. Register R5—Receiver Control Register
34
Register
R5—B7
P17CTL
(0)
R5
R5
R5
P21CTL
R5—B6
B(0—5)
(0)
Bit
B6
B7
RIL0—RIL5
R5—B5
(continued)
Symbol
P21CTL
P17CTL
RIL5
(0)
R5—B4
Receiver Interrupt Level. These bits determine when a receiver
full (RF) interrupt is triggered. The value programmed in RIL equals
the number of bytes in the receive FIFO which triggers an RF inter-
rupt. For example, a code of 001111 means an interrupt is gener-
ated when the receive FIFO contains 15 or more bytes. The code
000000 is a special case and means an interrupt is generated only
when the receive FIFO is actually full.
Pin 21 Control. This bit controls the functionality of pin 21. When
this bit is set to 1, pin 21 is configured as DRB, and received data is
clocked by CLKX. When this bit is cleared to 0, pin 21 is configured
as CLKR and provides the timing for received data.
Pin 17 Control. This bit controls the functionality of pin 17. When
this bit is cleared to 0, pin 17 is configured as DXB output. In this
configuration, data is transmitted on DXB. When this bit is set to 1,
pin 17 is configured as
(R7—B6). In this configuration, data can only be transmitted on
TDM highway A through the DXA pin (pin 19). If HWYEN (R0—B7)
is 0,
RIL4
(0)
TCSA
is continuously low.
R5—B3
RIL3
(0)
TCSA
Name/Function
R5—B2
. This overrides the setting of DXBC
RIL2
(0)
R5—B1
Lucent Technologies Inc.
RIL1
(0)
Data Sheet
April 1997
R5—B0
RIL0
(0)