PCA9506DGG,512 NXP Semiconductors, PCA9506DGG,512 Datasheet - Page 13

• Manufacturer Part Number: PCA9506DGG,512
• Description: IC I/O EXPANDER I2C 40B 56TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9506DGG,512

• Package / Case: 56-TSSOP
• Interface: I²C
• Number Of I /o: 40
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA9506
• Number Of Lines (input / Output): 40.0 / 40.0
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 500 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5.5 V
• Logic Type: I/O Expander
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 40.0
• Number Of Output Lines: 40.0
• Output Current: 50 mA
• Output Voltage: 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3354-5; 935280798512; PCA9506DGG

NXP Semiconductors
PCA9505_9506
Product data sheet
7.6 Interrupt output (INT)
7.7 Output enable input (OE)
7.8 Live insertion
7.9 Standby
The open-drain active LOW interrupt is activated when one of the port pins changes state
and the port pin is configured as an input and the interrupt on it is not masked. The
interrupt is deactivated when the port pin input returns to its previous state or the Input
Port register is read.
Remark: Changing an I/O from an output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
Only a read of the Input Port register that contains the bit(s) image of the input(s) that
generated the interrupt clears the interrupt condition.
If more than one input register changed state before a read of the Input Port register is
initiated, the interrupt is cleared when all the input registers containing all the inputs that
changed are read.
Example: If IO0_5, IO2_3, and IO3_7 change state at the same time, the interrupt is
cleared only when INREG0, INREG2, and INREG3 are read.
The active LOW output enable pin allows to enable or disable all the I/Os at the same
time. When a LOW level is applied to the OE pin, all the I/Os configured as outputs are
enabled and the logic value programmed in their respective OP registers is applied to the
pins. When a HIGH level is applied to the OE pin, all the I/Os configured as outputs are
3-stated.
For applications requiring LED blinking with brightness control, this pin can be used to
control the brightness by applying a high frequency PWM signal on the OE pin. LEDs can
be blinked using the Output Port registers and can be dimmed using the PWM signal on
the OE pin thus controlling the brightness by adjusting the duty cycle.
The PCA9505/06 are fully specified for live insertion applications using I
3-states, robust state machine, and 50 ns noise filter. The I
outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state’s circuitry places the outputs in the high-impedance state
during power-up and power-down, which prevents driver conflict and bus contention.
The robust state machine does not respond until it sees a valid START condition and the
50 ns noise filter will filter out any insertion glitches. The PCA9505/06 will not cause
corruption of active data on the bus, nor will the device be damaged or cause damage to
devices already on the bus when similar featured devices are being used.
The PCA9505/06 goes into standby when the I
lower than 1 μA (typical).
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 3 August 2010
40-bit I
2
2
C-bus is idle. Standby supply current is
C-bus I/O port with RESET, OE and INT
OFF
circuitry disables the
PCA9505/06
© NXP B.V. 2010. All rights reserved.
OFF
, power-up
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