PCA9506DGG,512 NXP Semiconductors, PCA9506DGG,512 Datasheet - Page 22

• Manufacturer Part Number: PCA9506DGG,512
• Description: IC I/O EXPANDER I2C 40B 56TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9506DGG,512

• Package / Case: 56-TSSOP
• Interface: I²C
• Number Of I /o: 40
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA9506
• Number Of Lines (input / Output): 40.0 / 40.0
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 500 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5.5 V
• Logic Type: I/O Expander
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 40.0
• Number Of Output Lines: 40.0
• Output Current: 50 mA
• Output Voltage: 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3354-5; 935280798512; PCA9506DGG

NXP Semiconductors
Table 10.
V
[1]
12. Dynamic characteristics
Table 11.
PCA9505_9506
Product data sheet
Symbol
Inputs A0, A1, A2
V
V
I
C
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Port timing
t
t
t
t
t
Interrupt timing
t
t
LI
SCL
BUF
HD;STA
SU;STA
SU;STO
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
HIGH
f
r
SP
en
dis
v(Q)
su(D)
h(D)
v(INT_N)
rst(INT_N)
DD
IL
IH
i
= 2.3 V to 5.5 V; V
V
DD
must be lowered to 0.2 V in order to reset part.
Parameter
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START
condition
set-up time for a repeated START
condition
set-up time for STOP condition
data hold time
data valid acknowledge time
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL
signals
rise time of both SDA and SCL
signals
pulse width of spikes that must be
suppressed by the input filter
enable time
disable time
data output valid time
data input set-up time
data input hold time
valid time on pin INT_N
reset time on pin INT_N
Static characteristics
Dynamic characteristics
Parameter
LOW-level input voltage
HIGH-level input voltage
input leakage current
input capacitance
SS
= 0 V; T
[3]
amb
…continued
=
−
[2]
40
All information provided in this document is subject to legal disclaimers.
°
C to +85
Conditions
Conditions
output
output
Rev. 4 — 3 August 2010
°
C; unless otherwise specified.
[4][5]
[4][5]
[1]
[7]
40-bit I
Standard mode
Min
250
100
4.7
4.0
4.7
4.0
0.1
0.1
4.7
4.0
0.5
0
0
-
-
-
-
-
-
-
-
I
2
2
C-bus
C-bus I/O port with RESET, OE and INT
1000
3.45
3.45
Max
100
300
250
50
80
40
4
4
-
-
-
-
-
-
-
-
-
-
Min
−0.5
0.7V
−1
-
DD
20 + 0.1C
20 + 0.1C
Fast mode I
PCA9505/06
Typ
-
-
-
3.5
Min
100
100
1.3
0.6
0.6
0.6
0.1
0.1
1.3
0.6
0.5
0
0
-
-
-
-
-
-
b
b
[6]
[6]
© NXP B.V. 2010. All rights reserved.
2
Max
+0.3V
5.5
+1
5
C-bus
Max
250
400
300
300
0.9
0.9
50
80
40
4
4
-
-
-
-
-
-
-
-
-
-
DD
22 of 34
Unit
kHz
μs
μs
μs
μs
ns
μs
μs
ns
μs
μs
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
Unit
V
V
μA
pF