ATmega3290P Atmel Corporation, ATmega3290P Datasheet - Page 15

• Manufacturer Part Number: ATmega3290P
• Manufacturer: Atmel Corporation

Specifications of ATmega3290P

• Flash (kbytes): 32 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6.6.1
6.7
8021G–AVR–03/11
Instruction Execution Timing
SPH and SPL – Stack pointer High and Stack Pointer Low
This section describes the general access timing concepts for instruction execution. The
Atmel
source for the chip. No internal clock division is used.
Figure 6-4
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6-4.
Figure 6-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
2nd Instruction Execute
®
3rd Instruction Execute
1st Instruction Execute
AVR
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
shows the internal timing concept for the Register File. In a single clock cycle an ALU
shows the parallel instruction fetches and instruction executions enabled by the Har-
®
CPU is driven by the CPU clock clk
The Parallel Instruction Fetches and Instruction Executions
SP15
R/W
R/W
SP7
15
7
0
0
clk
CPU
SP14
R/W
R/W
SP6
14
6
0
0
SP13
R/W
R/W
SP5
13
5
0
0
T1
SP12
R/W
R/W
SP4
12
4
0
0
CPU
, directly generated from the selected clock
T2
SP11
R/W
R/W
SP3
11
3
0
0
ATmega329P/3290P
SP10
SP2
R/W
R/W
10
2
0
0
T3
SP9
SP1
R/W
R/W
9
1
0
0
SP8
SP0
R/W
R/W
8
0
0
0
T4
SPH
SPL
15