ATmega3290P Atmel Corporation, ATmega3290P Datasheet - Page 241

• Manufacturer Part Number: ATmega3290P
• Manufacturer: Atmel Corporation

Specifications of ATmega3290P

• Flash (kbytes): 32 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.5
23.5.1
8021G–AVR–03/11
Register Description
LCDCRA – LCD Control and Status Register A
• Bit 7 – LCDEN: LCD Enable
Writing this bit to one enables the LCD Controller/Driver. By writing it to zero, the LCD is turned
off immediately. Turning the LCD Controller/Driver off while driving a display, enables ordinary
port function, and DC voltage can be applied to the display if ports are configured as output. It is
recommended to drive output to ground if the LCD Controller/Driver is disabled to discharge the
display.
• Bit 6 – LCDAB: LCD Low Power Waveform
When LCDAB is written logic zero, the default waveform is output on the LCD pins. When
LCDAB is written logic one, the Low Power Waveform is output on the LCD pins. If this bit is
modified during display operation the change takes place at the beginning of a new frame.
• Bit 5 – Reserved Bit
This bit is reserved and will always read as zero.
• Bit 4 – LCDIF: LCD Interrupt Flag
This bit is set by hardware at the beginning of a new frame, at the same time as the display data
is updated. The LCD Start of Frame Interrupt is executed if the LCDIE bit and the I-bit in SREG
are set. LCDIF is cleared by hardware when executing the corresponding Interrupt Handling
Vector. Alternatively, writing a logical one to the flag clears LCDIF. Beware that if doing a Read-
Modify-Write on LCDCRA, a pending interrupt can be disabled. If Low Power Waveform is
selected the Interrupt Flag is set every second frame.
• Bit 3 – LCDIE: LCD Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the LCD Start of Frame Interrupt is
enabled.
• Bit 2 – LCDBD: LCD Buffer Disable
The intermediate voltage levels in the LCD are generated by an internal resistive voltage divider
and passed through buffer to increase the current driving capability. By writing this bit to one the
buffers are turned off and bypassed, resulting in decreased power consumption. The total resis-
tance of the voltage divider is nominally 400 kΩ between LCDCAP and GND.
• Bit 1 – LCDCCD: LCD Contrast Control Disable
Writing this bit to one disables the internal power supply for the LCD driver. The desired voltage
must be applied to the LCDCAP pin from an external power supply. To avoid conflict between
internal and external power supply, this bit must be written as '1' prior to or simultaneously with
writing '1' to the LCDEN bit.
Bit
(0xE4)
Read/Write
Initial Value
LCDEN
R/W
7
0
LCDAB
R/W
6
0
R
5
–
0
LCDIF
R/W
4
0
LCDIE
R/W
3
0
ATmega329P/3290P
LCDBD
R
2
0
LCDCCD
R
1
0
LCDBL
R/W
0
0
LCDCRA
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