DS21348

Manufacturer Part NumberDS21348
Description3.3V E1/T1/J1 Line Interface
ManufacturerDallas Semiconducotr
DS21348 datasheet
 


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6. CONTROL REGISTERS
CCR1 (00H): COMMON CONTROL REGISTER 1
(MSB)
ETS
NRZE
RCLA
SYMBOL
POSITION
ETS
CCR1.7
NRZE
CCR1.6
RCLA
CCR1.5
ECUE
CCR1.4
JAMUX
CCR1.3
TTOJ
CCR1.2
TTOR
CCR1.1
LOTCMC
CCR1.0
ECUE
JAMUX
TTOJ
DESCRIPTION
E1/T1 Select.
0 = E1
1 = T1
NRZ Enable.
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a
positive going pulse when device receives a BPV, CV, or EXZ.
Receive Carrier Loss Alternate Criteria.
0 = RCL declared upon 255 (E1) or 192 (T1) consecutive zeros
1 = RCL declared upon 2048 (E1) or 1544 (T1) consecutive
zeros
Error Counter Update Enable. A 0 to 1 transition forces the
next clock cycle to load the error counter registers with the
latest counts and reset the counters. The user must wait a
minimum of two clocks cycles (976ns for E1 and 1296ns for
T1) before reading the error count registers to allow for a proper
update. See Section 6 for details.
Jitter Attenuator MUX. Controls the source for JACLK. See .
0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at
MCLK)
1 = JACLK sourced from internal PLL (2.048MHz at MCLK)
TCLK to JACLK. Internally connects TCLK to JACLK. See .
0 = disabled
1 = enabled
TCLK to RCLK. Internally connects TCLK to RCLK. See .
0 = disabled
1 = enabled
Loss Of Transmit Clock Mux Control. Determines whether
the transmit logic should switch to JACLK if the TCLK input
should fail to transition. See .
0 = do not switch to JACLK if TCLK stops
1 = switch to JACLK if TCLK stops
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(LSB)
TTOR
LOTCMC