DS21348

Manufacturer Part NumberDS21348
Description3.3V E1/T1/J1 Line Interface
ManufacturerDallas Semiconducotr
DS21348 datasheet
 


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INTERNAL RX TERMINATION SELECT Table 6-5
RT1
(CCR5.1)
0
0
1
1
CCR6 (05H): COMMON CONTROL REGISTER 6
(MSB)
LLB
RLB
ARLBE
SYMBOL
POSITION
LLB
CCR6.7
RLB
CCR6.6
ARLBE
CCR6.5
ALB
CCR6.4
RJAB
CCR6.3
RT0
INTERNAL RECEIVE
(CCR5.0)
TERMINATION CONFIGURATION
0
Internal receive-side termination disabled
1
Internal receive-side 120W enabled
0
Internal receive-side 100W enabled
1
Internal receive-side 75W enabled
ALB
RJAB
DESCRIPTION
Local Loopback. In Local Loopback (LLB), transmit data will
be looped back to the receive path passing through the jitter
attenuator if it is enabled. Data in the transmit path will act as
normal. See for details.
0 = loopback disabled
1 = loopback enabled
Remote Loopback. In Remote Loopback (RLB), data output
from the clock/data recovery circuitry will be looped back to the
transmit path passing through the jitter attenuator if it is
enabled. Data in the receive path will act as normal while data
presented at TPOS and TNEG will be ignored. See for details.
0 = loopback disabled
1 = loopback enabled
Automatic Remote Loopback Enable & Reset. When this bit
is set high, the device will automatically go into remote
loopback when it detects loop up code programmed into the
Receive Loop Up Code Definition Registers (RUPCD1 and
RUPCD2) for a minimum of 5 seconds and it will also set the
RIR2.1 status bit. Once in a RLB state, it will remain in this
state until it has detected the loop code programmed into the
Receive Loop Down Code Definition Registers (RDNCD1 and
RDNCD2) for a minimum of 5 seconds at which point it will
force the device out of RLB and clear RIR2.1. The automatic
RLB circuitry can be reset by toggling this bit from a 1 to a 0.
The action of the automatic remote loopback circuitry is
logically OR’ed with the RLB (CCR6.6) control bit (i.e. either
one can cause a RLB to occur).
Analog Loopback. In Analog Loopback (ALB), signals at
TTIP and TRING will be internally connected to RTIP and
RRING. The incoming signals, from the line, at RTIP and
RRING will be ignored. The signals at TTIP and TRING will
be transmitted as normal. See for more details.
0 = loopback disabled
1 = loopback enabled
RCLK Jitter Attenuator Bypass. This control bit allows the
33 of 73
(LSB)
ECRS2
ECRS1
ECRS0