DS21348

Manufacturer Part NumberDS21348
Description3.3V E1/T1/J1 Line Interface
ManufacturerDallas Semiconducotr
DS21348 datasheet
 


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6.1
Device Power-Up and Reset
The DS21348 will reset itself upon power-up setting all writeable registers to 00h and clear the status and
information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After the
power supplies have settled following power-up, initialize all control registers to the desired settings, then
toggle the LIRST bit (CCR3.2). At anytime, the DS21348 can be reset to the default settings by bringing
HRST* (pin 29) low (level triggered) or by powering down and powering up again.
CCR4 (03H): COMMON CONTROL REGISTER 4
(MSB)
L2
L1
SYMBOL
POSITION
L2
CCR4.7
L1
CCR4.6
L0
CCR4.5
EGL
CCR4.4
JAS
CCR4.3
JABDS
CCR4.2
DJA
CCR4.1
TPD
CCR4.0
RECEIVE SENSITIVITY SETTINGS Table 6-2
EGL
(CCR4.4)
0
1
1
0
L0
EGL
JAS
DESCRIPTION
Line Build Out Select Bit 2. Sets the transmitter build out; see
Table 9-1 for E1 and Table 9-2 for T1.
Line Build Out Select Bit 1. Sets the transmitter build out; see
Table 9-1 for E1 and Table 9-2 for T1.
Line Build Out Select Bit 0. Sets the transmitter build out; see
Table 9-1 for E1 and Table 9-2 for T1.
Receive Equalizer Gain Limit. This bit controls the sensitivity
of the receive equalizer. See Table 6-2.
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Transmit Power-Down.
0 = normal transmitter operation
1 = powers down the transmitter and 3-states the TTIP and
TRING pins
ETS
(CCR1.7)
0 (E1)
0 (E1)
1 (T1)
1 (T1)
31 of 73
JABDS
DJA
RECEIVE SENSITIVITY
-12dB (short haul)
-43dB (long haul)
-30dB (limited long haul)
-36dB (long haul)
(LSB)
TPD