DS21Q41BTN Dallas Semiconducotr, DS21Q41BTN Datasheet - Page 19

• Manufacturer Part Number: DS21Q41BTN
• Description: Quad T1 Framer
• Manufacturer: Dallas Semiconducotr

FRAMER LOOPBACK
When CCR1.0 is set to a 1, the DS21Q41B will enter a Framer LoopBack (FLB) mode. This loopback is
useful in testing and debugging applications. In FLB, the DS21Q41B will loop data from the transmit
side back to the receive side. When FLB is enabled, the following will occur:
1. An unframed all 1s code will be transmitted at TPOS and TNEG.
2. Data at RPOS and RNEG will be ignored.
3. All receive side signals will take on timing synchronous with TCLK instead of RCLK.
CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex)
(MSB)
TFM
SYMBOL
TSLC96
RSLC96
TB8ZS
RB8ZS
RFDL
TFDL
RFM
TFM
TB8ZS
POSITION
CCR2.7
CCR2.6
CCR2.5
CCR2.4
CCR2.3
CCR2.2
CCR2.1
CCR2.0
TSLC96
NAME AND DESCRIPTION
Transmit Frame Mode Select.
0=D4 framing mode
1=ESF framing mode
Transmit B8ZS Enable.
0=B8ZS disabled
1=B8ZS enabled
Transmit SLC-96/Fs Bit Insertion Enable.
0=SLC-96 disabled
1=SLC-96 enabled
Transmit 0 Stuffer Enable.
0=0 stuffer disabled
1=0 stuffer enabled
Receive Frame Mode Select.
0=D4 framing mode
1=ESF framing mode
Receive B8ZS Enable.
0=B8ZS disabled
1=B8ZS enabled
Receive SLC-96 Enable.
0=SLC-96 disabled
1=SLC-96 enabled
Receive 0 Destuffer Enable.
0=0 destuffer disabled
1=0 destuffer enabled
TFDL
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RFM
RB8ZS
RSLC96
RFDL
DS21Q41B
(LSB)