DS21Q41BTN Dallas Semiconducotr, DS21Q41BTN Datasheet - Page 56

• Manufacturer Part Number: DS21Q41BTN
• Description: Quad T1 Framer
• Manufacturer: Dallas Semiconducotr

TRANSMIT LINE INTERFACE SIDE AC TIMING Figure 13-7
AC CHARACTERISTICS -
TRANSMIT SIDE
See Figures 13-7 to 13-9 for details.
NOTES:
1. TSYSCLK = 1.544 MHz.
2. TSYSCLK = 2.048 MHz.
3. TSYNC in input mode.
PARAMETER
TCLK Period
TCLK Pulse Width
TSYSCLK Period
TSYSCLK Pulse Width
TSER, TSYNC and TLINK Set Up to
TCLK Falling or TSER, TFSYNC Set
Up to TSYSCLK Falling
TSYNC, TFSYNC Pulse Width
TSER, TSYNC and TLINK Hold from
TCLK Falling or TSER
TCLK or TSYSCLK Rise and Fall Times
Delay TCLK to TPOS/TNEG Valid
Delay TCLK to TCHCLK or TSYSCLK
to TCHCLK
Delay TCLK to TCHBLK or TSYSCLK
to TCHBLK
Delay TCLK to TSYNC
Delay TCLK to TLCLK
-40 C to +85 C; V
SYMBOL
(0 C to 70 C; V
t
R
56 of 61
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PW
HD
DD
CH
CP
CL
SH
SL
SU
D1
D2
D3
D4
SP
SP
, t
F
MIN
75
75
50
50
20
50
20
DD
DD
=5V
TYP
=5V
648
648
488
10% for DS21Q41BTN)
10% for DS21Q41BT;
MAX
25
75
75
75
75
75
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS21Q41B
NOTES
1
2
3