DS21Q41BTN Dallas Semiconducotr, DS21Q41BTN Datasheet - Page 39

• Manufacturer Part Number: DS21Q41BTN
• Description: Quad T1 Framer
• Manufacturer: Dallas Semiconducotr

DS21Q41B
10.0 ELASTIC STORES OPERATION
Each framer within the DS21Q41B contains dual two-frame (386 bits) elastic stores, one for the receive
direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can
be used to rate convert the T1 data stream to 2.048 Mbps (or a multiple of 2.048 Mbps) which is the E1
rate. Secondly, they can be used to absorb the differences in frequency and phase between the T1 data
stream and an asynchronous (i.e., not frequency locked) backplane clock (which can be 1.544 MHz or
2.048 MHz ). Both elastic stores contain full controlled slip capability which is necessary for this second
purpose. The receive side elastic store can be enabled via CCR1.2 and the transmit side elastic store is
enabled via CCR1.7. The elastic stores can be forced to a known depth via the Elastic Store Reset bit
(CCR3.6). Toggling the CCR3.6 bit forces the read and write pointers into opposite frames. Both elastic
stores within the DS21Q41B are fully independent and no restrictions apply to the sourcing of the various
clocks that are applied to them. The transmit side elastic store can be enabled whether the receive elastic
store is enabled or disabled and vice versa. Also, each elastic store can interface to either a 1.544 MHz or
2.048 MHz backplane without regard to the backplane rate the other elastic store is interfacing.
10.1 Receive Side
If the receive side elastic store is enabled (CCR1.2=1), then the user must provide either a 1.544 MHz
(CCR1.3=0) or 2.048 MHz (CCR1.3=1) clock at the RSYSCLK pin. The user has the option of either
providing a frame sync at the RSYNC pin (RCR2.3=1) or having the RSYNC pin provide a pulse on
frame boundaries (RCR2.3=0). If the user wishes to obtain pulses at the frame boundary, then RCR2.4
must be set to 0, and if the user wishes to have pulses occur at the multiframe boundary, then RCR2.4
must be set to 1. The DS21Q41B will always indicate frame boundaries via the RFSYNC output whether
the elastic store is enabled or not. If the elastic store is enabled, then multiframe boundaries will be
indicated via the RMSYNC output. If the user selects to apply a 2.048 MHz clock to the SYSCLK pin,
then the data output at RSER will be forced to all 1s every fourth channel and the F-bit will be deleted.
Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be forced to a
1. Also, in 2.048 MHz applications, the RCHBLK output will be forced high during the same channels as
the RSER pin. See Section 12 for more details. This is useful in T1 to CEPT (E1) conversion
applications. If the 386-bit elastic buffer either fills or empties, a controlled slip will occur. If the buffer
empties, then a full frame of data (193 bits) will be repeated at RSER and the SR1.4 and RIR1.3 bits will
be set to a 1. If the buffer fills, then a full frame of data will be deleted and the SR1.4 and RIR1.4 bits will
be set to a 1.
10.2 Transmit Side
The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic
store is enabled via CCR1.7. A 1.544 MHz (CCR1.4=0) or 2.048 MHz (CCR1.4=1) clock can be applied
to the TSYSCLK input. If the user selects to apply a 2.048 MHz clock to the TSYSCLK pin, then the data
output at TSER will be ignored every fourth channel. Hence channels 1, 5, 9, 13, 17, 21, 25, and 29
(timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be ignored. The user must supply a 8 kHz frame sync pulse
to the TFSYNC input. Also, in 2.048 MHz applications the TCHBLK output will be forced high during
the channels ignored by the DS21Q41B. See Section 12 for more details. Controlled slips in the transmit
elastic store are reported in the RIR2.3 bit and the direction of the slip is reported in the RIR2.5 and
RIR2.4 bits.
10.3 Minimum Delay Synchronous SYSCLK Mode
In applications where the DS21Q41B is connected to backplanes that are frequency locked to the
recovered T1 clock (i.e., the RCLK output), the full two-frame depth of the onboard elastic stores is really
not needed. In fact, in some delay sensitive applications, the normal two-frame depth may be excessive. If
the CCR3.7 bit is set to 1, then the receive elastic store (and also the transmit elastic store if it is enabled)
will be forced to a maximum depth of 32 bits instead of the normal 386 bits. In this mode, RSYSCLK
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