DS21Q41BTN Dallas Semiconducotr, DS21Q41BTN Datasheet - Page 40

• Manufacturer Part Number: DS21Q41BTN
• Description: Quad T1 Framer
• Manufacturer: Dallas Semiconducotr

and TSYSCLK must be tied together and they must be frequency locked to RCLK. All of the slip
contention logic in the DS21Q41B is disabled (since slips cannot occur). Also, since the buffer depth is
no longer two frames deep, the DS21Q41B must be set up to source either a frame pulse at the RSYNC
pin and this output must be tied to the TFSYNC input. On power-up after the RSYSCLK and TSYSCLK
signals have locked to the RCLK signal, the elastic store reset bit (CCR3.6) should be toggled from a 0 to
a 1 to insure proper operation.
11.0 RECEIVE MARK REGISTERS
The DS21Q41B has the ability to replace the incoming data, on a channel-by-channel basis with either an
idle code (7F Hex) or the digital milliwatt code which is a 8-byte repeating pattern that represents a 1 kHz
sine wave (1E/0B/0B/1E/9E/8B/8B/9E). The RCR2.7 bit will determine which code is used. Each bit in
the RMRs, represents a particular channel. If a bit is set to a one, then the receive data in that channel will
be replaced with one of the two codes. If a bit is set to 0, no replacement occurs.
RMR1/RMR2/RMR3: RECEIVE MARK REGISTERS (Address=2D to 2F Hex)
(MSB)
CH16
CH24
CH8
SYMBOL
CH24
CH1
CH15
CH23
CH7
POSITION
RCBR3.7
RCBR1.0
CH14
CH22
CH6
CH13
CH21
CH5
NAME AND DESCRIPTION
Receive Channel Blocking Registers.
0=do not affect the receive data associated with this channel
1=replace the receive data associated with this channel with either
the idle code or the digital milliwatt code (depends on the
(RCR2.7 bit)
CH12
CH20
CH4
40 of 61
CH11
CH19
CH3
CH10
CH18
CH2
CH17
CH1
CH9
(LSB)
RMR1 (2D)
RMR2 (2E)
RMR3 (2F)
DS21Q41B