DS21Q41BTN Dallas Semiconducotr, DS21Q41BTN Datasheet - Page 26

• Manufacturer Part Number: DS21Q41BTN
• Description: Quad T1 Framer
• Manufacturer: Dallas Semiconducotr

DS21Q41B ALARM SET & CLEAR CRITERIA Table 4-2
NOTES:
1. The definition of Blue Alarm (or Alarm Indication Signal) is an unframed all 1s signal. Blue alarm
2. ANSI specifications use a different nomenclature than the DS21Q41B does; the following terms are
LOOP UP/DOWN CODE DETECTION
Bits SR1.7 and SR1.6 will indicate when either the standard “loop up” or “loop down” codes are being
received by the DS21Q41B. When a loop up code has been received for 5 seconds, the CPE is expected
to loop the recovered data (without correcting BPVs) back to the source. The loop down code indicates
that the loopback should be discontinued. See the AT&T publication TR 62411 for more details. The
DS21Q41B will detect the loop up/down codes in both framed and unframed circumstances with bit error
rates as high as 10**-2. The loop code detector has a nominal integration period of 48 ms. Hence, after
about 48 ms of receiving either code, the proper status bit will be set to a 1. After this initial indication, it
is recommend that the software poll the DS21Q41B every 100 ms to 500 ms until 5 seconds has elapsed
to insure that the code is continuously present.
Blue Alarm (AIS)
(see note 1 below)
Yellow Alarm (RAI)
1. D4 bit 2 mode (RCR2.2=0)
2. D4 12
(RCR2.2=1; this mode is also
referred to as the "Japanese
Yellow Alarm")
3. ESF mode
Red Alarm (RCL)
(this alarm is also referred to
as Loss of Signal)
detectors should be able to operate properly in the presence of a 10-3 error rate and they should not
falsely trigger on a framed all 1s signal. The blue alarm criteria in the DS21Q41B has been set to
achieve this performance. It is recommended that the RBL bit be qualified with the RLOS bit.
equivalent:
th
ALARM
F-bit mode
RBL=AIS
RCL=LOS
RLOS=LOF
RYEL=RAI
when over a 3 ms window, five
or less 0s are received
when bit 2 of 256 consecutive
channels is set to 0 for at least
254 occurrences
when the 12
to one for two consecutive
occurrences
when 16 consecutive patterns of
00FF appear in the FDL
when 192 consecutive 0s are
received
SET CRITERIA
th
framing bit is set
26 of 61
when over a 3 ms window, six or
more 0s are received
when bit 2 of 256 consecutive
channels is set to 0 for less than
254 occurrences
when the 12
0 for two consecutive occurrences
when 14 or less patterns of 00FF
hex out of 16 possible appear in
the FDL
when 14 or more ones out of 112
possible bit positions are received
starting with the first one received
CLEAR CRITERIA
th
framing bit is set to
DS21Q41B