cy28548 SpectraLinear Inc, cy28548 Datasheet - Page 19

• Manufacturer Part Number: cy28548
• Description: Clock Generator For Intel Crestline Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.5 September 16, 2008
.
Table 6. Output Driver Status during PCI-STOP# and CPU-STOP#
Table 7. Output Driver Status
.
Table 8. PLL3/SE Configuration Table
Single-ended Clocks Stoppable
Differential Clocks
Latches Open State
Powerdown
M1
GCLK_SEL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
B1b4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
Non stoppable
Stoppable
Non stoppable
Low
Low
Low
All Single-ended Clocks
w/o Strap
B1b3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
B1b2
Hi-z
Hi-z
Hi-z
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
w/ Strap
Driven low
Running
Clock driven high
Clock# driven low
Running
PCI_STOP# Asserted
B1b1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Low or 20K pulldown Low
Low or 20K pulldown Low
Low or 20K pulldown Low
All Differential Clocks except
Pin 17 MHz
27M_NSS
27M_NSS
27M_NSS
27M_NSS
27M_NSS
Clock
100
100
100
100
100
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
CPU1
Running
Running
Clock driven high
Clock# driven low
Running
CPU_STOP# Asserted
Pin 18 MHz
27M_SS
27M_SS
27M_SS
27M_SS
27M_SS
Clock#
100
100
100
100
100
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PLL3 Disabled
Spread (%)
Low or 20K pulldown Low
Running
Low or 20K pulldown Low
none
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.5
0.5
1.5
0.5
0.5
1.5
1
2
1
2
Clock
Driven low
Clock driven Low or 20K
pulldown
SMBus OE Disabled
SRC1 from SRC_Main
27M_NSS from PLL3
27M_NSS from PLL3
27M_NSS from PLL3
27M_NSS from PLL3
27M_NSS from PLL3
LCD_100 from PLL3
LCD_100 from PLL3
LCD_100 from PLL3
LCD_100 from PLL3
CPU1
CY28548
Comment
Page 19 of 30
Running
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Clock#