cy28548 SpectraLinear Inc, cy28548 Datasheet - Page 8

• Manufacturer Part Number: cy28548
• Description: Clock Generator For Intel Crestline Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.5 September 16, 2008
Byte 3: Control Register 3
Byte 4: Control Register 4
Byte 5: Control Register 5
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
@Pup
@Pup
@Pup
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
SRC[T/C]1/LCD_100M[T/C] Output enable for SRC1/LCD_100M
SRC[T/C]0/DOT96[T/C]
SRC[T/C]8/CPU2_ITP
SRC[T/C]2/SATA
PLL1_SS_EN
PLL3_SS_EN
CR#_A_SEL
CR#_B_SEL
SRC[T/C]10
SRC[T/C]11
CR#_C_EN
CR#_A_EN
CR#_B_EN
SRC[T/C]9
SRC[T/C]7
SRC[T/C]6
SRC[T/C]4
SRC[T/C]3
CPU[T/C]1
CPU[T/C]0
Reserved
Name
Name
Name
Output enable for SRC11
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC10
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC9
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC8 or CPU2_ITP
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC7
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC6
0 = Output Disabled, 1 = Output Enabled
Reserved
Output enable for SRC4
0 = Output Disabled, 1 = Output Enabled
Enable CR#_A (clk req)
0 = Disabled, 1 = Enabled,
Set CR#_A → SRC0 or SRC2
0 = CR#_A→SRC0, 1 = CR#_A→SRC2
Enable CR#_B(clk req)
0 = Disabled, 1 = Enabled,
Set CR#_B → SRC1 or SRC4
0 = CR#_B→SRC1, 1 = CR#_B→SRC4
Enable CR#_C (clk req)
0 = Disabled, 1 = Enabled
Output enable for SRC3
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC2/SATA
0 = Output Disabled, 1 = Output Enabled
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC0/DOT96
0 = Output Disabled, 1 = Output Enabled
Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
Enable PLL1s spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
Enable PLL3s spread modulation
0 = Spread Disabled, 1 = Spread Enabled
Description
Description
Description
CY28548
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