cy28548 SpectraLinear Inc, cy28548 Datasheet - Page 7

• Manufacturer Part Number: cy28548
• Description: Clock Generator For Intel Crestline Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.5 September 16, 2008
Control Registers
Byte 0: Control Register 0
Byte 1: Control Register 1
Byte 2: Control Register 2
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
HW
HW
HW
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
SRC_Main_SEL
PLL1_SS_DC
PLL3_SS_DC
PD_Restore
PLL3_CFB3
PLL3_CFB2
PLL3_CFB1
PLL3_CFB0
SRC0_SEL
SATA_SEL
iAMT_EN
Reserved
Reserved
Name
Name
Name
PCIF0
FS_C
FS_B
FS_A
PCI4
PCI3
PCI2
PCI1
PCI0
USB
REF
CPU Frequency Select Bit, set by HW
CPU Frequency Select Bit, set by HW
CPU Frequency Select Bit, set by HW
Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP
0 = Legacy Mode, 1 = iAMT Enabled
Reserved
Select source for SRC clock
0 = SRC_MAIN = PLL1, PLL3_CFG Table applies
1 = SRC_MAIN = PLL3, PLL3_CFG Table does not apply
Select source of SATA clock
Save Config. In powerdown
Select for SRC0 or DOT96
0 = SRC0, 1 = DOT96
When GCLK_SEL=0, this bit is 1. When GCLK_SEL=1, this bit is 0
Select for down or center SS
0 = Down spread, 1 = Center spread
Select for down or center SS
0 = Down spread, 1 = Center spread
Bit 4:1 only applies when SRC_Main_SEL = 0
SeeTable 8: PLL3 / SE configuration table
Reserved
Output enable for REF
0 = Output Disabled, 1 = Output Enabled
Output enable for USB
0 = Output Disabled, 1 = Output Enabled
Output enable for PCIF0
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI4
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI3
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI2
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI1
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI0
0 = Output Disabled, 1 = Output Enabled
0 = SATA = SRC_MAIN, 1= SATA = PLL2
0 = Config. Cleared, 1 = Config. Saved
Description
Description
Description
CY28548
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