mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 114

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mc68hc08qa24

Manufacturer Part Number
mc68hc08qa24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Clock Generator Module (CGM)
Technical Data
112
NOTE:
Exceeding the recommended maximum bus frequency or VCO
frequency can crash the MCU.
For proper operation,
5. Calculate the bus frequency, f
6. Using the value 4.9152 MHz for f
7. Calculate the VCO center-of-range frequency, f
f
your application, select another f
range multiplier, L. The linear range multiplier controls the
frequency range of the PLL.
center-of-range frequency is the midpoint between the minimum
and maximum frequencies attainable by the PLL.
BUSDES
Clock Generator Module (CGM)
Example: f
. If the calculated f
Example:
Example:
VRS
L
f
VRS
f
= 7 × 4.9152 MHz = 34.4 MHz
f
VRS
=
BUS
f
BUS
L
round
=
BUS
=
= L × f
f
VCLK
------------------------------- -
4.9152 MHz
=
32 MHz
------------------- -
BUS
32 MHz
is not within the tolerance limits of
f
----------- -
VCLK
4
BUSDES
4
f
------------ -
f
NOM
NOM
VCLK
, and compare f
NOM
f
-------------- -
NOM
2
, calculate the VCO linear
=
8 MHz
or another f
=
7
Freescale Semiconductor
VRS
BUS
MC68HC08QA24
. The
XCLK
with
.

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