mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 355

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

22.9.3 CPU Stop Mode
22.9.4 Programmable Wakeup Function
22.10 Timer Link
MC68HC08QA24
Freescale Semiconductor
NOTE:
A CPU STOP instruction will stop the crystal oscillator, thus shutting
down all system clocks. The user is responsible for ensuring that the
MSCAN08 is not active when the CPU goes into stop mode. To protect
the CAN bus system from fatal consequences of violations to this rule,
the MSCAN08 will drive the CANTx pin into a recessive state.
The recommended procedure is to bring the MSCAN08 into sleep mode
before the CPU STOP instruction is executed.
The MSCAN08 can be programmed to apply a low-pass filter function to
the CANRx input line while in internal sleep mode (see information on
control bit WUPM in
This feature can be used to protect the MSCAN08 from wakeup due to
short glitches on the CAN bus lines. Such glitches can result from
electromagnetic inference within noisy environments.
The MSCAN08 will generate a timer signal whenever a valid frame has
been received. Because the CAN specification defines a frame to be
valid if no errors occurred before the EOF field has been transmitted
successfully, the timer signal will be generated right after the EOF. A
pulse of one bit time is generated. As the MSCAN08 receiver engine also
receives the frames being sent by itself, a timer signal also will be
generated after a successful transmission.
The previously described timer signal can be routed into the on-chip
timer interface module (TIM). Under the control of the timer link enable
(TLNKEN) bit in the CMCR0 will this signal be connected to the timer n
channel m input.
The timer channel being used for the timer link is integration dependent.
CAN Controller
22.14.1 MSCAN08 Module Control
Register).
CAN Controller
Technical Data
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