mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 263

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mc68hc08qa24

Manufacturer Part Number
mc68hc08qa24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
18.11 Low-Power Modes
18.11.1 Wait Mode
18.11.2 Stop Mode
MC68HC08QA24
Freescale Semiconductor
By not resetting the control bits when SPE is low, the user can clear SPE
between transmissions without having to reset all control bits when SPE
is set back to high for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still
service these interrupts after the SPI has been disabled. The user can
disable the SPI by writing 0 to the SPE bit. The SPI also can be disabled
by a mode fault occurring in an SPI that was configured as a master with
the MODFEN bit set.
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
The SPI module remains active after the execution of a WAIT instruction.
In wait mode, the SPI module registers are not accessible by the CPU.
Any enabled CPU interrupt request from the SPI module can bring the
MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF
bit to generate CPU interrupt requests by setting the error interrupt
enable bit (ERRIE). (See
The SPI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect register conditions. SPI operation
resumes after the MCU exits stop mode. If stop mode is exited by reset,
any transfer in progress is aborted and the SPI is reset.
Serial Peripheral Interface (SPI)
18.8
Interrupts.)
Serial Peripheral Interface (SPI)
Technical Data
261

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