mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 262

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface (SPI)
18.10 Resetting the SPI
Technical Data
260
The transmit data buffer allows back-to-back transmissions without the
slave precisely timing its writes between transmissions as in a system
with a single data buffer. Also, if no new data is written to the data buffer,
the last value contained in the shift register is the next data word to be
transmitted.
For an idle master or idle slave that has no data loaded into its transmit
buffer, the SPTE is set again no more than two bus cycles after the
transmit buffer empties into the shift register. This allows the user to
queue up a 16-bit value to send. For an already active slave, the load of
the shift register cannot occur until the transmission is completed. This
implies that a back-to-back write to the transmit data register is not
possible. The SPTE indicates when the next write can occur.
Any system reset completely resets the SPI. Partial resets occur
whenever the SPI enable bit (SPE) is low. Whenever SPE is low, these
occur:
These additional items are reset only by a system reset:
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The SPTE flag is set.
Any transmission currently in progress is aborted.
The shift register is cleared.
The SPI state counter is cleared, making it ready for a new
complete transmission.
All the SPI port logic is defaulted back to being general-purpose
I/O.
All control bits in the SPCR register
All control bits in the SPSCR register (MODFEN, ERRIE, SPR1,
and SPR0)
The status flags SPRF, OVRF, and MODF
Serial Peripheral Interface (SPI)
Freescale Semiconductor
MC68HC08QA24