mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 52

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mc68hc08qa24

Manufacturer Part Number
mc68hc08qa24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Memory Map
Technical Data
50
Addr.
$003A
$0037
$0038
$0039
$0500
$0501
$0502
$0503
$0504
TIMB Channel 1 Register Low
CAN Receiver Flag Register
CAN Bus Timing Register 0
CAN Bus Timing Register 1
(ADICLK)
(ADSCR)
(CMCR0)
(CMCR1)
(CBTR0)
(CBTR1)
Analog-to-Digital Status
Analog-to-Digital Input
(ADR)
and Control Register
CAN Module Control
CAN Module Control
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 18)
Register Name
Analog-to-Digital
See page 334.
See page 279.
See page 282.
Clock Register
See page 282.
See page 365.
See page 367.
See page 368.
See page 369.
See page 371.
Data Register
Register 0
Register 1
(TBCH1L)
(CRFLG)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read: COCO
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
WUPF
ADIV2
SAMP
Bit 7
SJW1
Bit 7
AD7
R
R
R
R
R
0
0
0
0
0
0
0
0
0
RWRNIF TWRNIF
TSEG22 TSEG21
= Reserved
Memory Map
ADIV1
SJW0
AIEN
AD6
R
R
R
6
6
0
0
0
0
0
0
0
0
0
ADCO
ADIV0
BRP5
AD5
R
R
R
5
5
0
0
0
0
0
0
0
0
0
Indeterminate after reset
Indeterminate after reset
TSEG20
RERRIF
ADICLK
SYNCH
ADCH4
BRP4
AD4
U = Unaffected
4
R
R
R
4
1
0
0
0
0
0
0
0
TLNKEN
TSEG13 TSEG12 TSEG11 TSEG10
TERRIF
ADCH3
BRP3
AD3
R
R
R
3
3
1
0
0
0
0
0
0
0
0
BOFFIF
ADCH2
LOOPB
SLPAK
Freescale Semiconductor
BRP2
AD2
R
R
R
2
2
1
0
0
0
0
0
0
0
MC68HC08QA24
ADCH1
SLPRQ
WUPM
OVRIF
BRP1
AD1
R
R
1
1
1
0
0
0
0
0
0
0
CLKSRC
SFTRES
ADCH0
Bit 0
BRP0
Bit 0
RXF
AD0
R
R
1
0
0
0
0
0
0
0

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