mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 140

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
10.4.2.2 Computer Operating Properly (COP) Reset
10.4.2.3 Illegal Opcode Reset
10.4.2.4 Illegal Address Reset
10.4.2.5 Low-Voltage Inhibit (LVI) Reset
Technical Data
138
NOTE:
The overflow of the COP counter causes an internal reset and sets the
COP bit in the SIM reset status register (SRSR) if the COPD bit in the
CONFIG register ($001F) is at logic 0. (See
Operating Properly
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
A $9E opcode (pre-byte for SP instructions) followed by an $8E opcode
(stop instruction) generates a stop mode recovery reset.
If the stop enable bit, STOP, in the CONFIG register ($001F) is logic 0,
the SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset.
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset.
The low-voltage inhibit (LVI) module asserts its output to the SIM when
the V
status register (SRSR) is set and a chip reset is asserted if the LVIPWRD
and LVIRSTD bits in the CONFIG register are at logic 0. The RST pin will
be held low until the SIM counts 4096 CGMXCLK cycles after V
above V
from reset to allow the reset vector sequence to occur. (See
Low-Voltage Inhibit
DD
LVIR
voltage falls to the V
System Integration Module (SIM)
. Another 64 CGMXCLK cycles later, the CPU is released
(COP).)
(LVI).)
LVII
voltage. The LVI bit in the SIM reset
Section 14. Computer
Freescale Semiconductor
MC68HC08QA24
Section 11.
DD
rises