w83877atd Winbond Electronics Corp America, w83877atd Datasheet - Page 157

• Manufacturer Part Number: w83877atd
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

The control bit in the control register provides some special control functions over the hardware
event, or some special control over SCI event. Reserved or un-implemented control bits always
return zero, and writing to those bits should have no effect.
Table 8-4 lists the PM1 register block and the relative locations of the registers within it. The base
address of PM1 register block is named as PM1a_EVT_BLK in the ACPI specification. The base
address should range from 01,0000,0000
of PM1 register block should be set to 0 and the base address is in the 16-byte alignment.
Table 8-5 lists the GPE register block and the relative locations within it. The base address of power
management event block GPE is named as GPE0_BLK in the ACPI specification. The base address
should range from 01,0000,0000
address should be set to 0 and the base address is in the 8-byte alignment.
8.4.1 Power Management 1 Status Register 1 (PM1STS1)
Register Location:
Default Value:
Attribute:
Size:
0
1-3
4
5
6-7
Bit
TMR_STS
Reserved
BM_STS
GBL_STS
Reserved
Name
This bit is the timer carry status bit. This bit gets set anytime the bit 23 of the
24-bit counter changes (whenever the MSB changes from low to high or high
to low). While TMR_EN and TMR_STS are set, a power magement event is
raised. This bit is only set by hardware and can only be cleared by the
software writing a 1 to this bit position. Writing a 0 has no effect.
Reserved.
This is the bus master status bit. Writing a 1 to BM_CNTRL also sets
BM_STS. Writing a 1 clears this bit and also clears BM_CNTRL. Writing a 0
has no effect.
This is the global status bit. This bit is set when the BIOS want the attention
of the SCI handler. BIOS sets this bit by setting BIOS_RLS and can only be
cleared by software writing a 1 to this bit position. Writing a 1 to this bit
position also clears BIOS_RLS. Writing a 0 has no effect.
Reserved. These bits always return a value of zero.
<CR33> System I/O Space
00h
Read/write
8 bits
7
6
b
to 11,1111,1000
5
b
4
to 11,1111,0000
3
- 153 -
2
b
,i.e., 100H ~ 3F8H, where bit 0 of the base
Description
1
b
,i.e., 100H ~ 3F0H, where bit 1 and bit 0
0
Publication Release Date: April 1998
TMR_STS
Reserved
Reserved
Reserved
BM_STS
GBL_STS
Reserved
Reserved
W83877ATF
Version 0.51