w83977atf Winbond Electronics Corp America, w83977atf Datasheet - Page 179

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w83977atf

Manufacturer Part Number
w83977atf
Description
Winbond I/o
Manufacturer
Winbond Electronics Corp America
Datasheet

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9.3.12 Power Management 1 Timer 4 (PM1TMR4)
Register Location:
Default Value:
Attribute:
Size:
0-7
9.3.13 General Purpose Event 0 Status Register 1 (GP0STS1)
Register Location:
Default Value:
Attribute:
Size:
These bits indicate the status of the SCI input, which is set when the device's IRQ is raised. If the
corresponding enable bit in the SCI interrupt enable register (in GP0EN1) is set, an SCI interrupt is
raised and routed to the output pin. Wrinting a 1 clears the bit, and writing a 0 has no effect. If the bit
is not cleared, new IRQ to the SCI logic input is ignored and no SCI interrupt will be raised.
Bit
Reserved
Name
8 bits
8 bits
Reserved. These bits always return zeros.
<CR60,
00h
Read only
<CR62,
00h
Read/write
7
7
6
6
61> + BH System I/O Space
63> System I/O Space
5
5
4
4
3
3
-123 -
2
2
1
Description
1
0
0
URBSCISTS
URASCISTS
FDCSCISTS
PRTSCISTS
KBCSCISTS
MOUSCISTS
IRSCISTS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Publication Release Date:April 1998
W83977ATF
PRELIMINARY
Revision 0.53

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